1 /*
2 * Broadcom BCMSDH to SPI Protocol Conversion Layer
3 *
4 * Copyright (C) 1999-2009, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 * $Id: bcmsdspi.c,v 1.14.4.2.4.4.6.4 2009/04/13 19:18:36 Exp $
25 */
26
27 #include <typedefs.h>
28
29 #include <bcmdevs.h>
30 #include <bcmendian.h>
31 #include <bcmutils.h>
32 #include <osl.h>
33 #include <siutils.h>
34 #include <sdio.h> /* SDIO Device and Protocol Specs */
35 #include <sdioh.h> /* SDIO Host Controller Specification */
36 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
37 #include <sdiovar.h> /* ioctl/iovars */
38
39 #include <pcicfg.h>
40
41
42 #include <bcmsdspi.h>
43 #include <bcmspi.h>
44
45 #include <proto/sdspi.h>
46
47 #define SD_PAGE 4096
48
49 /* Globals */
50
51 uint sd_msglevel = SDH_ERROR_VAL;
52 uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
53 uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
54 uint sd_f2_blocksize = 512; /* Default blocksize */
55
56 uint sd_divisor = 2; /* Default 33MHz/2 = 16MHz for dongle */
57 uint sd_power = 1; /* Default to SD Slot powered ON */
58 uint sd_clock = 1; /* Default to SD Clock turned ON */
59 uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
60
61 uint sd_toctl = 7;
62
63 /* Prototypes */
64 static bool sdspi_start_power(sdioh_info_t *sd);
65 static int sdspi_set_highspeed_mode(sdioh_info_t *sd, bool HSMode);
66 static int sdspi_card_enablefuncs(sdioh_info_t *sd);
67 static void sdspi_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count);
68 static int sdspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd, uint32 arg,
69 uint32 *data, uint32 datalen);
70 static int sdspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
71 int regsize, uint32 *data);
72 static int sdspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
73 int regsize, uint32 data);
74 static int sdspi_driver_init(sdioh_info_t *sd);
75 static bool sdspi_reset(sdioh_info_t *sd, bool host_reset, bool client_reset);
76 static int sdspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
77 uint32 addr, int nbytes, uint32 *data);
78 static int sdspi_abort(sdioh_info_t *sd, uint func);
79
80 static int set_client_block_size(sdioh_info_t *sd, int func, int blocksize);
81
82 static uint8 sdspi_crc7(unsigned char* p, uint32 len);
83 static uint16 sdspi_crc16(unsigned char* p, uint32 len);
84 static int sdspi_crc_onoff(sdioh_info_t *sd, bool use_crc);
85
86 /*
87 * Public entry points & extern's
88 */
89 extern sdioh_info_t *
sdioh_attach(osl_t * osh,void * bar0,uint irq)90 sdioh_attach(osl_t *osh, void *bar0, uint irq)
91 {
92 sdioh_info_t *sd;
93
94 sd_trace(("%s\n", __FUNCTION__));
95 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
96 sd_err(("sdioh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
97 return NULL;
98 }
99 bzero((char *)sd, sizeof(sdioh_info_t));
100 sd->osh = osh;
101
102 if (spi_osinit(sd) != 0) {
103 sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
104 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
105 return NULL;
106 }
107
108 sd->bar0 = (uintptr)bar0;
109 sd->irq = irq;
110 sd->intr_handler = NULL;
111 sd->intr_handler_arg = NULL;
112 sd->intr_handler_valid = FALSE;
113
114 /* Set defaults */
115 sd->sd_blockmode = FALSE;
116 sd->use_client_ints = TRUE;
117 sd->sd_use_dma = FALSE; /* DMA Not supported */
118
119 /* Haven't figured out how to make bytemode work with dma */
120 if (!sd->sd_blockmode)
121 sd->sd_use_dma = 0;
122
123 if (!spi_hw_attach(sd)) {
124 sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
125 spi_osfree(sd);
126 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
127 return NULL;
128 }
129
130 if (sdspi_driver_init(sd) != SUCCESS) {
131 if (sdspi_driver_init(sd) != SUCCESS) {
132 sd_err(("%s:sdspi_driver_init() failed()\n", __FUNCTION__));
133 spi_hw_detach(sd);
134 spi_osfree(sd);
135 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
136 return (NULL);
137 }
138 }
139
140 if (spi_register_irq(sd, irq) != SUCCESS) {
141 sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
142 spi_hw_detach(sd);
143 spi_osfree(sd);
144 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
145 return (NULL);
146 }
147
148 sd_trace(("%s: Done\n", __FUNCTION__));
149 return sd;
150 }
151
152 extern SDIOH_API_RC
sdioh_detach(osl_t * osh,sdioh_info_t * sd)153 sdioh_detach(osl_t *osh, sdioh_info_t *sd)
154 {
155 sd_trace(("%s\n", __FUNCTION__));
156
157 if (sd) {
158 if (sd->card_init_done)
159 sdspi_reset(sd, 1, 1);
160
161 sd_info(("%s: detaching from hardware\n", __FUNCTION__));
162 spi_free_irq(sd->irq, sd);
163 spi_hw_detach(sd);
164 spi_osfree(sd);
165 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
166 }
167
168 return SDIOH_API_RC_SUCCESS;
169 }
170
171 /* Configure callback to client when we recieve client interrupt */
172 extern SDIOH_API_RC
sdioh_interrupt_register(sdioh_info_t * sd,sdioh_cb_fn_t fn,void * argh)173 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
174 {
175 sd_trace(("%s: Entering\n", __FUNCTION__));
176
177 sd->intr_handler = fn;
178 sd->intr_handler_arg = argh;
179 sd->intr_handler_valid = TRUE;
180
181 return SDIOH_API_RC_SUCCESS;
182 }
183
184 extern SDIOH_API_RC
sdioh_interrupt_deregister(sdioh_info_t * sd)185 sdioh_interrupt_deregister(sdioh_info_t *sd)
186 {
187 sd_trace(("%s: Entering\n", __FUNCTION__));
188
189 sd->intr_handler_valid = FALSE;
190 sd->intr_handler = NULL;
191 sd->intr_handler_arg = NULL;
192
193 return SDIOH_API_RC_SUCCESS;
194 }
195
196 extern SDIOH_API_RC
sdioh_interrupt_query(sdioh_info_t * sd,bool * onoff)197 sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
198 {
199 sd_trace(("%s: Entering\n", __FUNCTION__));
200
201 *onoff = sd->client_intr_enabled;
202
203 return SDIOH_API_RC_SUCCESS;
204 }
205
206 #if defined(DHD_DEBUG)
207 extern bool
sdioh_interrupt_pending(sdioh_info_t * sd)208 sdioh_interrupt_pending(sdioh_info_t *sd)
209 {
210 return 0;
211 }
212 #endif
213
214 uint
sdioh_query_iofnum(sdioh_info_t * sd)215 sdioh_query_iofnum(sdioh_info_t *sd)
216 {
217 return sd->num_funcs;
218 }
219
220 /* IOVar table */
221 enum {
222 IOV_MSGLEVEL = 1,
223 IOV_BLOCKMODE,
224 IOV_BLOCKSIZE,
225 IOV_DMA,
226 IOV_USEINTS,
227 IOV_NUMINTS,
228 IOV_NUMLOCALINTS,
229 IOV_HOSTREG,
230 IOV_DEVREG,
231 IOV_DIVISOR,
232 IOV_SDMODE,
233 IOV_HISPEED,
234 IOV_HCIREGS,
235 IOV_POWER,
236 IOV_CLOCK,
237 IOV_CRC
238 };
239
240 const bcm_iovar_t sdioh_iovars[] = {
241 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
242 {"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0 },
243 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
244 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0 },
245 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
246 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
247 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
248 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
249 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
250 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
251 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
252 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
253 {"sd_crc", IOV_CRC, 0, IOVT_UINT32, 0 },
254 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
255 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
256 {NULL, 0, 0, 0, 0 }
257 };
258
259 int
sdioh_iovar_op(sdioh_info_t * si,const char * name,void * params,int plen,void * arg,int len,bool set)260 sdioh_iovar_op(sdioh_info_t *si, const char *name,
261 void *params, int plen, void *arg, int len, bool set)
262 {
263 const bcm_iovar_t *vi = NULL;
264 int bcmerror = 0;
265 int val_size;
266 int32 int_val = 0;
267 bool bool_val;
268 uint32 actionid;
269
270 ASSERT(name);
271 ASSERT(len >= 0);
272
273 /* Get must have return space; Set does not take qualifiers */
274 ASSERT(set || (arg && len));
275 ASSERT(!set || (!params && !plen));
276
277 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
278
279 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
280 bcmerror = BCME_UNSUPPORTED;
281 goto exit;
282 }
283
284 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
285 goto exit;
286
287 /* Set up params so get and set can share the convenience variables */
288 if (params == NULL) {
289 params = arg;
290 plen = len;
291 }
292
293 if (vi->type == IOVT_VOID)
294 val_size = 0;
295 else if (vi->type == IOVT_BUFFER)
296 val_size = len;
297 else
298 val_size = sizeof(int);
299
300 if (plen >= (int)sizeof(int_val))
301 bcopy(params, &int_val, sizeof(int_val));
302
303 bool_val = (int_val != 0) ? TRUE : FALSE;
304
305 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
306 switch (actionid) {
307 case IOV_GVAL(IOV_MSGLEVEL):
308 int_val = (int32)sd_msglevel;
309 bcopy(&int_val, arg, val_size);
310 break;
311
312 case IOV_SVAL(IOV_MSGLEVEL):
313 sd_msglevel = int_val;
314 break;
315
316 case IOV_GVAL(IOV_BLOCKMODE):
317 int_val = (int32)si->sd_blockmode;
318 bcopy(&int_val, arg, val_size);
319 break;
320
321 case IOV_SVAL(IOV_BLOCKMODE):
322 si->sd_blockmode = (bool)int_val;
323 /* Haven't figured out how to make non-block mode with DMA */
324 if (!si->sd_blockmode)
325 si->sd_use_dma = 0;
326 break;
327
328 case IOV_GVAL(IOV_BLOCKSIZE):
329 if ((uint32)int_val > si->num_funcs) {
330 bcmerror = BCME_BADARG;
331 break;
332 }
333 int_val = (int32)si->client_block_size[int_val];
334 bcopy(&int_val, arg, val_size);
335 break;
336
337 case IOV_SVAL(IOV_BLOCKSIZE):
338 {
339 uint func = ((uint32)int_val >> 16);
340 uint blksize = (uint16)int_val;
341 uint maxsize;
342
343 if (func > si->num_funcs) {
344 bcmerror = BCME_BADARG;
345 break;
346 }
347
348 switch (func) {
349 case 0: maxsize = 32; break;
350 case 1: maxsize = BLOCK_SIZE_4318; break;
351 case 2: maxsize = BLOCK_SIZE_4328; break;
352 default: maxsize = 0;
353 }
354 if (blksize > maxsize) {
355 bcmerror = BCME_BADARG;
356 break;
357 }
358 if (!blksize) {
359 blksize = maxsize;
360 }
361
362 /* Now set it */
363 spi_lock(si);
364 bcmerror = set_client_block_size(si, func, blksize);
365 spi_unlock(si);
366 break;
367 }
368
369 case IOV_GVAL(IOV_DMA):
370 int_val = (int32)si->sd_use_dma;
371 bcopy(&int_val, arg, val_size);
372 break;
373
374 case IOV_SVAL(IOV_DMA):
375 si->sd_use_dma = (bool)int_val;
376 break;
377
378 case IOV_GVAL(IOV_USEINTS):
379 int_val = (int32)si->use_client_ints;
380 bcopy(&int_val, arg, val_size);
381 break;
382
383 case IOV_SVAL(IOV_USEINTS):
384 break;
385
386 case IOV_GVAL(IOV_DIVISOR):
387 int_val = (uint32)sd_divisor;
388 bcopy(&int_val, arg, val_size);
389 break;
390
391 case IOV_SVAL(IOV_DIVISOR):
392 sd_divisor = int_val;
393 if (!spi_start_clock(si, (uint16)sd_divisor)) {
394 sd_err(("set clock failed!\n"));
395 bcmerror = BCME_ERROR;
396 }
397 break;
398
399 case IOV_GVAL(IOV_POWER):
400 int_val = (uint32)sd_power;
401 bcopy(&int_val, arg, val_size);
402 break;
403
404 case IOV_SVAL(IOV_POWER):
405 sd_power = int_val;
406 break;
407
408 case IOV_GVAL(IOV_CLOCK):
409 int_val = (uint32)sd_clock;
410 bcopy(&int_val, arg, val_size);
411 break;
412
413 case IOV_SVAL(IOV_CLOCK):
414 sd_clock = int_val;
415 break;
416
417 case IOV_GVAL(IOV_CRC):
418 int_val = (uint32)sd_crc;
419 bcopy(&int_val, arg, val_size);
420 break;
421
422 case IOV_SVAL(IOV_CRC):
423 /* Apply new setting, but don't change sd_crc until
424 * after the CRC-mode is selected in the device. This
425 * is required because the software must generate a
426 * correct CRC for the CMD59 in order to be able to
427 * turn OFF the CRC.
428 */
429 sdspi_crc_onoff(si, int_val ? 1 : 0);
430 sd_crc = int_val;
431 break;
432
433 case IOV_GVAL(IOV_SDMODE):
434 int_val = (uint32)sd_sdmode;
435 bcopy(&int_val, arg, val_size);
436 break;
437
438 case IOV_SVAL(IOV_SDMODE):
439 sd_sdmode = int_val;
440 break;
441
442 case IOV_GVAL(IOV_HISPEED):
443 int_val = (uint32)sd_hiok;
444 bcopy(&int_val, arg, val_size);
445 break;
446
447 case IOV_SVAL(IOV_HISPEED):
448 sd_hiok = int_val;
449
450 if (!sdspi_set_highspeed_mode(si, (bool)sd_hiok)) {
451 sd_err(("Failed changing highspeed mode to %d.\n", sd_hiok));
452 bcmerror = BCME_ERROR;
453 return ERROR;
454 }
455 break;
456
457 case IOV_GVAL(IOV_NUMINTS):
458 int_val = (int32)si->intrcount;
459 bcopy(&int_val, arg, val_size);
460 break;
461
462 case IOV_GVAL(IOV_NUMLOCALINTS):
463 int_val = (int32)si->local_intrcount;
464 bcopy(&int_val, arg, val_size);
465 break;
466
467 case IOV_GVAL(IOV_HOSTREG):
468 {
469 break;
470 }
471
472 case IOV_SVAL(IOV_HOSTREG):
473 {
474 sd_err(("IOV_HOSTREG unsupported\n"));
475 break;
476 }
477
478 case IOV_GVAL(IOV_DEVREG):
479 {
480 sdreg_t *sd_ptr = (sdreg_t *)params;
481 uint8 data;
482
483 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
484 bcmerror = BCME_SDIO_ERROR;
485 break;
486 }
487
488 int_val = (int)data;
489 bcopy(&int_val, arg, sizeof(int_val));
490 break;
491 }
492
493 case IOV_SVAL(IOV_DEVREG):
494 {
495 sdreg_t *sd_ptr = (sdreg_t *)params;
496 uint8 data = (uint8)sd_ptr->value;
497
498 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
499 bcmerror = BCME_SDIO_ERROR;
500 break;
501 }
502 break;
503 }
504
505
506 default:
507 bcmerror = BCME_UNSUPPORTED;
508 break;
509 }
510 exit:
511
512 return bcmerror;
513 }
514
515 extern SDIOH_API_RC
sdioh_cfg_read(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)516 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
517 {
518 SDIOH_API_RC status;
519 /* No lock needed since sdioh_request_byte does locking */
520 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
521 return status;
522 }
523
524 extern SDIOH_API_RC
sdioh_cfg_write(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)525 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
526 {
527 /* No lock needed since sdioh_request_byte does locking */
528 SDIOH_API_RC status;
529 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
530 return status;
531 }
532
533 extern SDIOH_API_RC
sdioh_cis_read(sdioh_info_t * sd,uint func,uint8 * cisd,uint32 length)534 sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
535 {
536 uint32 count;
537 int offset;
538 uint32 foo;
539 uint8 *cis = cisd;
540
541 sd_trace(("%s: Func = %d\n", __FUNCTION__, func));
542
543 if (!sd->func_cis_ptr[func]) {
544 bzero(cis, length);
545 return SDIOH_API_RC_FAIL;
546 }
547
548 spi_lock(sd);
549 *cis = 0;
550 for (count = 0; count < length; count++) {
551 offset = sd->func_cis_ptr[func] + count;
552 if (sdspi_card_regread (sd, 0, offset, 1, &foo) < 0) {
553 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
554 spi_unlock(sd);
555 return SDIOH_API_RC_FAIL;
556 }
557 *cis = (uint8)(foo & 0xff);
558 cis++;
559 }
560 spi_unlock(sd);
561 return SDIOH_API_RC_SUCCESS;
562 }
563
564 extern SDIOH_API_RC
sdioh_request_byte(sdioh_info_t * sd,uint rw,uint func,uint regaddr,uint8 * byte)565 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
566 {
567 int status;
568 uint32 cmd_arg;
569 uint32 rsp5;
570
571 spi_lock(sd);
572
573 cmd_arg = 0;
574 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
575 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
576 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
577 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
578 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, rw == SDIOH_READ ? 0 : *byte);
579
580 sd_trace(("%s: rw=%d, func=%d, regaddr=0x%08x\n", __FUNCTION__, rw, func, regaddr));
581
582 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
583 SDIOH_CMD_52, cmd_arg, NULL, 0)) != SUCCESS) {
584 spi_unlock(sd);
585 return status;
586 }
587
588 sdspi_cmd_getrsp(sd, &rsp5, 1);
589 if (rsp5 != 0x00) {
590 sd_err(("%s: rsp5 flags is 0x%x func=%d\n",
591 __FUNCTION__, rsp5, func));
592 /* ASSERT(0); */
593 spi_unlock(sd);
594 return SDIOH_API_RC_FAIL;
595 }
596
597 if (rw == SDIOH_READ)
598 *byte = sd->card_rsp_data >> 24;
599
600 spi_unlock(sd);
601 return SDIOH_API_RC_SUCCESS;
602 }
603
604 extern SDIOH_API_RC
sdioh_request_word(sdioh_info_t * sd,uint cmd_type,uint rw,uint func,uint addr,uint32 * word,uint nbytes)605 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
606 uint32 *word, uint nbytes)
607 {
608 int status;
609
610 spi_lock(sd);
611
612 if (rw == SDIOH_READ)
613 status = sdspi_card_regread(sd, func, addr, nbytes, word);
614 else
615 status = sdspi_card_regwrite(sd, func, addr, nbytes, *word);
616
617 spi_unlock(sd);
618 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
619 }
620
621 extern SDIOH_API_RC
sdioh_request_buffer(sdioh_info_t * sd,uint pio_dma,uint fix_inc,uint rw,uint func,uint addr,uint reg_width,uint buflen_u,uint8 * buffer,void * pkt)622 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
623 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
624 {
625 int len;
626 int buflen = (int)buflen_u;
627 bool fifo = (fix_inc == SDIOH_DATA_FIX);
628
629 spi_lock(sd);
630
631 ASSERT(reg_width == 4);
632 ASSERT(buflen_u < (1 << 30));
633 ASSERT(sd->client_block_size[func]);
634
635 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
636 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
637 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
638
639 /* Break buffer down into blocksize chunks:
640 * Bytemode: 1 block at a time.
641 */
642 while (buflen > 0) {
643 if (sd->sd_blockmode) {
644 /* Max xfer is Page size */
645 len = MIN(SD_PAGE, buflen);
646
647 /* Round down to a block boundry */
648 if (buflen > sd->client_block_size[func])
649 len = (len/sd->client_block_size[func]) *
650 sd->client_block_size[func];
651 } else {
652 /* Byte mode: One block at a time */
653 len = MIN(sd->client_block_size[func], buflen);
654 }
655
656 if (sdspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
657 spi_unlock(sd);
658 return SDIOH_API_RC_FAIL;
659 }
660 buffer += len;
661 buflen -= len;
662 if (!fifo)
663 addr += len;
664 }
665 spi_unlock(sd);
666 return SDIOH_API_RC_SUCCESS;
667 }
668
669 static int
sdspi_abort(sdioh_info_t * sd,uint func)670 sdspi_abort(sdioh_info_t *sd, uint func)
671 {
672 uint8 spi_databuf[] = { 0x74, 0x80, 0x00, 0x0C, 0xFF, 0x95, 0xFF, 0xFF,
673 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
674 uint8 spi_rspbuf[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
675 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
676 int err = 0;
677
678 sd_err(("Sending SPI Abort to F%d\n", func));
679 spi_databuf[4] = func & 0x7;
680 /* write to function 0, addr 6 (IOABORT) func # in 3 LSBs. */
681 spi_sendrecv(sd, spi_databuf, spi_rspbuf, sizeof(spi_databuf));
682
683 return err;
684 }
685
686 extern int
sdioh_abort(sdioh_info_t * sd,uint fnum)687 sdioh_abort(sdioh_info_t *sd, uint fnum)
688 {
689 int ret;
690
691 spi_lock(sd);
692 ret = sdspi_abort(sd, fnum);
693 spi_unlock(sd);
694
695 return ret;
696 }
697
698 int
sdioh_start(sdioh_info_t * sd,int stage)699 sdioh_start(sdioh_info_t *sd, int stage)
700 {
701 return SUCCESS;
702 }
703
704 int
sdioh_stop(sdioh_info_t * sd)705 sdioh_stop(sdioh_info_t *sd)
706 {
707 return SUCCESS;
708 }
709
710
711 /*
712 * Private/Static work routines
713 */
714 static bool
sdspi_reset(sdioh_info_t * sd,bool host_reset,bool client_reset)715 sdspi_reset(sdioh_info_t *sd, bool host_reset, bool client_reset)
716 {
717 if (!sd)
718 return TRUE;
719
720 spi_lock(sd);
721 /* Reset client card */
722 if (client_reset && (sd->adapter_slot != -1)) {
723 if (sdspi_card_regwrite(sd, 0, SDIOD_CCCR_IOABORT, 1, 0x8) != SUCCESS)
724 sd_err(("%s: Cannot write to card reg 0x%x\n",
725 __FUNCTION__, SDIOD_CCCR_IOABORT));
726 else
727 sd->card_rca = 0;
728 }
729
730 /* The host reset is a NOP in the sd-spi case. */
731 if (host_reset) {
732 sd->sd_mode = SDIOH_MODE_SPI;
733 }
734 spi_unlock(sd);
735 return TRUE;
736 }
737
738 static int
sdspi_host_init(sdioh_info_t * sd)739 sdspi_host_init(sdioh_info_t *sd)
740 {
741 sdspi_reset(sd, 1, 0);
742
743 /* Default power on mode is SD1 */
744 sd->sd_mode = SDIOH_MODE_SPI;
745 sd->polled_mode = TRUE;
746 sd->host_init_done = TRUE;
747 sd->card_init_done = FALSE;
748 sd->adapter_slot = 1;
749
750 return (SUCCESS);
751 }
752
753 #define CMD0_RETRIES 3
754 #define CMD5_RETRIES 10
755
756 static int
get_ocr(sdioh_info_t * sd,uint32 * cmd_arg,uint32 * cmd_rsp)757 get_ocr(sdioh_info_t *sd, uint32 *cmd_arg, uint32 *cmd_rsp)
758 {
759 uint32 rsp5;
760 int retries, status;
761
762 /* First issue a CMD0 to get the card into SPI mode. */
763 for (retries = 0; retries <= CMD0_RETRIES; retries++) {
764 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
765 SDIOH_CMD_0, *cmd_arg, NULL, 0)) != SUCCESS) {
766 sd_err(("%s: No response to CMD0\n", __FUNCTION__));
767 continue;
768 }
769
770 sdspi_cmd_getrsp(sd, &rsp5, 1);
771
772 if (GFIELD(rsp5, SPI_RSP_ILL_CMD)) {
773 printf("%s: Card already initialized (continuing)\n", __FUNCTION__);
774 break;
775 }
776
777 if (GFIELD(rsp5, SPI_RSP_IDLE)) {
778 printf("%s: Card in SPI mode\n", __FUNCTION__);
779 break;
780 }
781 }
782
783 if (retries > CMD0_RETRIES) {
784 sd_err(("%s: Too many retries for CMD0\n", __FUNCTION__));
785 return ERROR;
786 }
787
788 /* Get the Card's Operation Condition. */
789 /* Occasionally the board takes a while to become ready. */
790 for (retries = 0; retries <= CMD5_RETRIES; retries++) {
791 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
792 SDIOH_CMD_5, *cmd_arg, NULL, 0)) != SUCCESS) {
793 sd_err(("%s: No response to CMD5\n", __FUNCTION__));
794 continue;
795 }
796
797 printf("CMD5 response data was: 0x%08x\n", sd->card_rsp_data);
798
799 if (GFIELD(sd->card_rsp_data, RSP4_CARD_READY)) {
800 printf("%s: Card ready\n", __FUNCTION__);
801 break;
802 }
803 }
804
805 if (retries > CMD5_RETRIES) {
806 sd_err(("%s: Too many retries for CMD5\n", __FUNCTION__));
807 return ERROR;
808 }
809
810 *cmd_rsp = sd->card_rsp_data;
811
812 sdspi_crc_onoff(sd, sd_crc ? 1 : 0);
813
814 return (SUCCESS);
815 }
816
817 static int
sdspi_crc_onoff(sdioh_info_t * sd,bool use_crc)818 sdspi_crc_onoff(sdioh_info_t *sd, bool use_crc)
819 {
820 uint32 args;
821 int status;
822
823 args = use_crc ? 1 : 0;
824 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
825 SDIOH_CMD_59, args, NULL, 0)) != SUCCESS) {
826 sd_err(("%s: No response to CMD59\n", __FUNCTION__));
827 }
828
829 sd_info(("CMD59 response data was: 0x%08x\n", sd->card_rsp_data));
830
831 sd_err(("SD-SPI CRC turned %s\n", use_crc ? "ON" : "OFF"));
832 return (SUCCESS);
833 }
834
835 static int
sdspi_client_init(sdioh_info_t * sd)836 sdspi_client_init(sdioh_info_t *sd)
837 {
838 uint8 fn_ints;
839
840 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
841
842 /* Start at ~400KHz clock rate for initialization */
843 if (!spi_start_clock(sd, 128)) {
844 sd_err(("spi_start_clock failed\n"));
845 return ERROR;
846 }
847
848 if (!sdspi_start_power(sd)) {
849 sd_err(("sdspi_start_power failed\n"));
850 return ERROR;
851 }
852
853 if (sd->num_funcs == 0) {
854 sd_err(("%s: No IO funcs!\n", __FUNCTION__));
855 return ERROR;
856 }
857
858 sdspi_card_enablefuncs(sd);
859
860 set_client_block_size(sd, 1, BLOCK_SIZE_4318);
861 fn_ints = INTR_CTL_FUNC1_EN;
862
863 if (sd->num_funcs >= 2) {
864 set_client_block_size(sd, 2, sd_f2_blocksize /* BLOCK_SIZE_4328 */);
865 fn_ints |= INTR_CTL_FUNC2_EN;
866 }
867
868 /* Enable/Disable Client interrupts */
869 /* Turn on here but disable at host controller */
870 if (sdspi_card_regwrite(sd, 0, SDIOD_CCCR_INTEN, 1,
871 (fn_ints | INTR_CTL_MASTER_EN)) != SUCCESS) {
872 sd_err(("%s: Could not enable ints in CCCR\n", __FUNCTION__));
873 return ERROR;
874 }
875
876 /* Switch to High-speed clocking mode if both host and device support it */
877 sdspi_set_highspeed_mode(sd, (bool)sd_hiok);
878
879 /* After configuring for High-Speed mode, set the desired clock rate. */
880 if (!spi_start_clock(sd, (uint16)sd_divisor)) {
881 sd_err(("spi_start_clock failed\n"));
882 return ERROR;
883 }
884
885 sd->card_init_done = TRUE;
886
887 return SUCCESS;
888 }
889
890 static int
sdspi_set_highspeed_mode(sdioh_info_t * sd,bool HSMode)891 sdspi_set_highspeed_mode(sdioh_info_t *sd, bool HSMode)
892 {
893 uint32 regdata;
894 int status;
895 bool hsmode;
896
897 if (HSMode == TRUE) {
898
899 sd_err(("Attempting to enable High-Speed mode.\n"));
900
901 if ((status = sdspi_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
902 1, ®data)) != SUCCESS) {
903 return status;
904 }
905 if (regdata & SDIO_SPEED_SHS) {
906 sd_err(("Device supports High-Speed mode.\n"));
907
908 regdata |= SDIO_SPEED_EHS;
909
910 sd_err(("Writing %08x to Card at %08x\n",
911 regdata, SDIOD_CCCR_SPEED_CONTROL));
912 if ((status = sdspi_card_regwrite(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
913 1, regdata)) != BCME_OK) {
914 return status;
915 }
916
917 hsmode = 1;
918
919 sd_err(("High-speed clocking mode enabled.\n"));
920 }
921 else {
922 sd_err(("Device does not support High-Speed Mode.\n"));
923 hsmode = 0;
924 }
925 } else {
926 if ((status = sdspi_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
927 1, ®data)) != SUCCESS) {
928 return status;
929 }
930
931 regdata = ~SDIO_SPEED_EHS;
932
933 sd_err(("Writing %08x to Card at %08x\n",
934 regdata, SDIOD_CCCR_SPEED_CONTROL));
935 if ((status = sdspi_card_regwrite(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
936 1, regdata)) != BCME_OK) {
937 return status;
938 }
939
940 sd_err(("Low-speed clocking mode enabled.\n"));
941 hsmode = 0;
942 }
943
944 spi_controller_highspeed_mode(sd, hsmode);
945
946 return TRUE;
947 }
948
949 bool
sdspi_start_power(sdioh_info_t * sd)950 sdspi_start_power(sdioh_info_t *sd)
951 {
952 uint32 cmd_arg;
953 uint32 cmd_rsp;
954
955 sd_trace(("%s\n", __FUNCTION__));
956
957 /* Get the Card's Operation Condition. Occasionally the board
958 * takes a while to become ready
959 */
960
961 cmd_arg = 0;
962 if (get_ocr(sd, &cmd_arg, &cmd_rsp) != SUCCESS) {
963 sd_err(("%s: Failed to get OCR; bailing\n", __FUNCTION__));
964 return FALSE;
965 }
966
967 sd_err(("mem_present = %d\n", GFIELD(cmd_rsp, RSP4_MEM_PRESENT)));
968 sd_err(("num_funcs = %d\n", GFIELD(cmd_rsp, RSP4_NUM_FUNCS)));
969 sd_err(("card_ready = %d\n", GFIELD(cmd_rsp, RSP4_CARD_READY)));
970 sd_err(("OCR = 0x%x\n", GFIELD(cmd_rsp, RSP4_IO_OCR)));
971
972 /* Verify that the card supports I/O mode */
973 if (GFIELD(cmd_rsp, RSP4_NUM_FUNCS) == 0) {
974 sd_err(("%s: Card does not support I/O\n", __FUNCTION__));
975 return ERROR;
976 }
977
978 sd->num_funcs = GFIELD(cmd_rsp, RSP4_NUM_FUNCS);
979
980 /* Examine voltage: Arasan only supports 3.3 volts,
981 * so look for 3.2-3.3 Volts and also 3.3-3.4 volts.
982 */
983
984 if ((GFIELD(cmd_rsp, RSP4_IO_OCR) & (0x3 << 20)) == 0) {
985 sd_err(("This client does not support 3.3 volts!\n"));
986 return ERROR;
987 }
988
989
990 return TRUE;
991 }
992
993 static int
sdspi_driver_init(sdioh_info_t * sd)994 sdspi_driver_init(sdioh_info_t *sd)
995 {
996 sd_trace(("%s\n", __FUNCTION__));
997
998 if ((sdspi_host_init(sd)) != SUCCESS) {
999 return ERROR;
1000 }
1001
1002 if (sdspi_client_init(sd) != SUCCESS) {
1003 return ERROR;
1004 }
1005
1006 return SUCCESS;
1007 }
1008
1009 static int
sdspi_card_enablefuncs(sdioh_info_t * sd)1010 sdspi_card_enablefuncs(sdioh_info_t *sd)
1011 {
1012 int status;
1013 uint32 regdata;
1014 uint32 regaddr, fbraddr;
1015 uint8 func;
1016 uint8 *ptr;
1017
1018 sd_trace(("%s\n", __FUNCTION__));
1019 /* Get the Card's common CIS address */
1020 ptr = (uint8 *) &sd->com_cis_ptr;
1021 for (regaddr = SDIOD_CCCR_CISPTR_0; regaddr <= SDIOD_CCCR_CISPTR_2; regaddr++) {
1022 if ((status = sdspi_card_regread (sd, 0, regaddr, 1, ®data)) != SUCCESS)
1023 return status;
1024
1025 *ptr++ = (uint8) regdata;
1026 }
1027
1028 /* Only the lower 17-bits are valid */
1029 sd->com_cis_ptr &= 0x0001FFFF;
1030 sd->func_cis_ptr[0] = sd->com_cis_ptr;
1031 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
1032
1033 /* Get the Card's function CIS (for each function) */
1034 for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
1035 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
1036 ptr = (uint8 *) &sd->func_cis_ptr[func];
1037 for (regaddr = SDIOD_FBR_CISPTR_0; regaddr <= SDIOD_FBR_CISPTR_2; regaddr++) {
1038 if ((status = sdspi_card_regread (sd, 0, regaddr + fbraddr, 1, ®data))
1039 != SUCCESS)
1040 return status;
1041
1042 *ptr++ = (uint8) regdata;
1043 }
1044
1045 /* Only the lower 17-bits are valid */
1046 sd->func_cis_ptr[func] &= 0x0001FFFF;
1047 sd_info(("%s: Function %d CIS Ptr = 0x%x\n",
1048 __FUNCTION__, func, sd->func_cis_ptr[func]));
1049 }
1050
1051 sd_info(("%s: write ESCI bit\n", __FUNCTION__));
1052 /* Enable continuous SPI interrupt (ESCI bit) */
1053 sdspi_card_regwrite(sd, 0, SDIOD_CCCR_BICTRL, 1, 0x60);
1054
1055 sd_info(("%s: enable f1\n", __FUNCTION__));
1056 /* Enable function 1 on the card */
1057 regdata = SDIO_FUNC_ENABLE_1;
1058 if ((status = sdspi_card_regwrite(sd, 0, SDIOD_CCCR_IOEN, 1, regdata)) != SUCCESS)
1059 return status;
1060
1061 sd_info(("%s: done\n", __FUNCTION__));
1062 return SUCCESS;
1063 }
1064
1065 /* Read client card reg */
1066 static int
sdspi_card_regread(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1067 sdspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1068 {
1069 int status;
1070 uint32 cmd_arg;
1071 uint32 rsp5;
1072
1073 cmd_arg = 0;
1074
1075 if ((func == 0) || (regsize == 1)) {
1076 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
1077 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
1078 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SDIOH_XFER_TYPE_READ);
1079 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
1080 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, 0);
1081
1082 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_52, cmd_arg, NULL, 0))
1083 != SUCCESS)
1084 return status;
1085
1086 sdspi_cmd_getrsp(sd, &rsp5, 1);
1087
1088 if (rsp5 != 0x00)
1089 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
1090 __FUNCTION__, rsp5, func));
1091
1092 *data = sd->card_rsp_data >> 24;
1093 } else {
1094 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, regsize);
1095 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
1096 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
1097 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
1098 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, regaddr);
1099 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_READ);
1100
1101 sd->data_xfer_count = regsize;
1102
1103 /* sdspi_cmd_issue() returns with the command complete bit
1104 * in the ISR already cleared
1105 */
1106 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_53, cmd_arg, NULL, 0))
1107 != SUCCESS)
1108 return status;
1109
1110 sdspi_cmd_getrsp(sd, &rsp5, 1);
1111
1112 if (rsp5 != 0x00)
1113 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
1114 __FUNCTION__, rsp5, func));
1115
1116 *data = sd->card_rsp_data;
1117 if (regsize == 2) {
1118 *data &= 0xffff;
1119 }
1120
1121 sd_info(("%s: CMD53 func %d, addr 0x%x, size %d, data 0x%08x\n",
1122 __FUNCTION__, func, regaddr, regsize, *data));
1123
1124
1125 }
1126
1127 return SUCCESS;
1128 }
1129
1130 /* write a client register */
1131 static int
sdspi_card_regwrite(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 data)1132 sdspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
1133 {
1134 int status;
1135 uint32 cmd_arg, rsp5, flags;
1136
1137 cmd_arg = 0;
1138
1139 if ((func == 0) || (regsize == 1)) {
1140 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
1141 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
1142 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
1143 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
1144 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, data & 0xff);
1145 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_52, cmd_arg, NULL, 0))
1146 != SUCCESS)
1147 return status;
1148
1149 sdspi_cmd_getrsp(sd, &rsp5, 1);
1150 flags = GFIELD(rsp5, RSP5_FLAGS);
1151 if (flags && (flags != 0x10))
1152 sd_err(("%s: rsp5.rsp5.flags = 0x%x, expecting 0x10\n",
1153 __FUNCTION__, flags));
1154 }
1155 else {
1156 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, regsize);
1157 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
1158 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
1159 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
1160 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, regaddr);
1161 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
1162
1163 sd->data_xfer_count = regsize;
1164 sd->cmd53_wr_data = data;
1165
1166 sd_info(("%s: CMD53 func %d, addr 0x%x, size %d, data 0x%08x\n",
1167 __FUNCTION__, func, regaddr, regsize, data));
1168
1169 /* sdspi_cmd_issue() returns with the command complete bit
1170 * in the ISR already cleared
1171 */
1172 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_53, cmd_arg, NULL, 0))
1173 != SUCCESS)
1174 return status;
1175
1176 sdspi_cmd_getrsp(sd, &rsp5, 1);
1177
1178 if (rsp5 != 0x00)
1179 sd_err(("%s: rsp5 flags = 0x%x, expecting 0x00\n",
1180 __FUNCTION__, rsp5));
1181
1182 }
1183 return SUCCESS;
1184 }
1185
1186 void
sdspi_cmd_getrsp(sdioh_info_t * sd,uint32 * rsp_buffer,int count)1187 sdspi_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count /* num 32 bit words */)
1188 {
1189 *rsp_buffer = sd->card_response;
1190 }
1191
1192 int max_errors = 0;
1193
1194 #define SPI_MAX_PKT_LEN 768
1195 uint8 spi_databuf[SPI_MAX_PKT_LEN];
1196 uint8 spi_rspbuf[SPI_MAX_PKT_LEN];
1197
1198 /* datalen is used for CMD53 length only (0 for sd->data_xfer_count) */
1199 static int
sdspi_cmd_issue(sdioh_info_t * sd,bool use_dma,uint32 cmd,uint32 arg,uint32 * data,uint32 datalen)1200 sdspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd, uint32 arg,
1201 uint32 *data, uint32 datalen)
1202 {
1203 uint32 cmd_reg;
1204 uint32 cmd_arg = arg;
1205 uint8 cmd_crc = 0x95; /* correct CRC for CMD0 and don't care for others. */
1206 uint16 dat_crc;
1207 uint8 cmd52data = 0;
1208 uint32 i, j;
1209 uint32 spi_datalen = 0;
1210 uint32 spi_pre_cmd_pad = 0;
1211 uint32 spi_max_response_pad = 128;
1212
1213 cmd_reg = 0;
1214 cmd_reg = SFIELD(cmd_reg, SPI_DIR, 1);
1215 cmd_reg = SFIELD(cmd_reg, SPI_CMD_INDEX, cmd);
1216
1217 if (GFIELD(cmd_arg, CMD52_RW_FLAG) == 1) { /* Same for CMD52 and CMD53 */
1218 cmd_reg = SFIELD(cmd_reg, SPI_RW, 1);
1219 }
1220
1221 switch (cmd) {
1222 case SDIOH_CMD_59: /* CRC_ON_OFF (SPI Mode Only) - Response R1 */
1223 cmd52data = arg & 0x1;
1224 case SDIOH_CMD_0: /* Set Card to Idle State - No Response */
1225 case SDIOH_CMD_5: /* Send Operation condition - Response R4 */
1226 sd_trace(("%s: CMD%d\n", __FUNCTION__, cmd));
1227 spi_datalen = 44;
1228 spi_pre_cmd_pad = 12;
1229 spi_max_response_pad = 28;
1230 break;
1231
1232 case SDIOH_CMD_3: /* Ask card to send RCA - Response R6 */
1233 case SDIOH_CMD_7: /* Select card - Response R1 */
1234 case SDIOH_CMD_15: /* Set card to inactive state - Response None */
1235 sd_err(("%s: CMD%d is invalid for SPI Mode.\n", __FUNCTION__, cmd));
1236 return ERROR;
1237 break;
1238
1239 case SDIOH_CMD_52: /* IO R/W Direct (single byte) - Response R5 */
1240 cmd52data = GFIELD(cmd_arg, CMD52_DATA);
1241 cmd_arg = arg;
1242 cmd_reg = SFIELD(cmd_reg, SPI_FUNC, GFIELD(cmd_arg, CMD52_FUNCTION));
1243 cmd_reg = SFIELD(cmd_reg, SPI_ADDR, GFIELD(cmd_arg, CMD52_REG_ADDR));
1244 /* Display trace for byte write */
1245 if (GFIELD(cmd_arg, CMD52_RW_FLAG) == 1) {
1246 sd_trace(("%s: CMD52: Wr F:%d @0x%04x=%02x\n",
1247 __FUNCTION__,
1248 GFIELD(cmd_arg, CMD52_FUNCTION),
1249 GFIELD(cmd_arg, CMD52_REG_ADDR),
1250 cmd52data));
1251 }
1252
1253 spi_datalen = 32;
1254 spi_max_response_pad = 28;
1255
1256 break;
1257 case SDIOH_CMD_53: /* IO R/W Extended (multiple bytes/blocks) */
1258 cmd_arg = arg;
1259 cmd_reg = SFIELD(cmd_reg, SPI_FUNC, GFIELD(cmd_arg, CMD53_FUNCTION));
1260 cmd_reg = SFIELD(cmd_reg, SPI_ADDR, GFIELD(cmd_arg, CMD53_REG_ADDR));
1261 cmd_reg = SFIELD(cmd_reg, SPI_BLKMODE, 0);
1262 cmd_reg = SFIELD(cmd_reg, SPI_OPCODE, GFIELD(cmd_arg, CMD53_OP_CODE));
1263 cmd_reg = SFIELD(cmd_reg, SPI_STUFF0, (sd->data_xfer_count>>8));
1264 cmd52data = (uint8)sd->data_xfer_count;
1265
1266 /* Set upper bit in byte count if necessary, but don't set it for 512 bytes. */
1267 if ((sd->data_xfer_count > 255) && (sd->data_xfer_count < 512)) {
1268 cmd_reg |= 1;
1269 }
1270
1271 if (GFIELD(cmd_reg, SPI_RW) == 1) { /* Write */
1272 spi_max_response_pad = 32;
1273 spi_datalen = (sd->data_xfer_count + spi_max_response_pad) & 0xFFFC;
1274 } else { /* Read */
1275
1276 spi_max_response_pad = 32;
1277 spi_datalen = (sd->data_xfer_count + spi_max_response_pad) & 0xFFFC;
1278 }
1279 sd_trace(("%s: CMD53: %s F:%d @0x%04x len=0x%02x\n",
1280 __FUNCTION__,
1281 (GFIELD(cmd_reg, SPI_RW) == 1 ? "Wr" : "Rd"),
1282 GFIELD(cmd_arg, CMD53_FUNCTION),
1283 GFIELD(cmd_arg, CMD53_REG_ADDR),
1284 cmd52data));
1285 break;
1286
1287 default:
1288 sd_err(("%s: Unknown command %d\n", __FUNCTION__, cmd));
1289 return ERROR;
1290 }
1291
1292 /* Set up and issue the SDIO command */
1293 memset(spi_databuf, SDSPI_IDLE_PAD, spi_datalen);
1294 spi_databuf[spi_pre_cmd_pad + 0] = (cmd_reg & 0xFF000000) >> 24;
1295 spi_databuf[spi_pre_cmd_pad + 1] = (cmd_reg & 0x00FF0000) >> 16;
1296 spi_databuf[spi_pre_cmd_pad + 2] = (cmd_reg & 0x0000FF00) >> 8;
1297 spi_databuf[spi_pre_cmd_pad + 3] = (cmd_reg & 0x000000FF);
1298 spi_databuf[spi_pre_cmd_pad + 4] = cmd52data;
1299
1300 /* Generate CRC7 for command, if CRC is enabled, otherwise, a
1301 * default CRC7 of 0x95, which is correct for CMD0, is used.
1302 */
1303 if (sd_crc) {
1304 cmd_crc = sdspi_crc7(&spi_databuf[spi_pre_cmd_pad], 5);
1305 }
1306 spi_databuf[spi_pre_cmd_pad + 5] = cmd_crc;
1307 #define SPI_STOP_TRAN 0xFD
1308
1309 /* for CMD53 Write, put the data into the output buffer */
1310 if ((cmd == SDIOH_CMD_53) && (GFIELD(cmd_arg, CMD53_RW_FLAG) == 1)) {
1311 if (datalen != 0) {
1312 spi_databuf[spi_pre_cmd_pad + 9] = SDSPI_IDLE_PAD;
1313 spi_databuf[spi_pre_cmd_pad + 10] = SDSPI_START_BLOCK;
1314
1315 for (i = 0; i < sd->data_xfer_count; i++) {
1316 spi_databuf[i + 11 + spi_pre_cmd_pad] = ((uint8 *)data)[i];
1317 }
1318 if (sd_crc) {
1319 dat_crc = sdspi_crc16(&spi_databuf[spi_pre_cmd_pad+11], i);
1320 } else {
1321 dat_crc = 0xAAAA;
1322 }
1323 spi_databuf[i + 11 + spi_pre_cmd_pad] = (dat_crc >> 8) & 0xFF;
1324 spi_databuf[i + 12 + spi_pre_cmd_pad] = dat_crc & 0xFF;
1325 } else if (sd->data_xfer_count == 2) {
1326 spi_databuf[spi_pre_cmd_pad + 9] = SDSPI_IDLE_PAD;
1327 spi_databuf[spi_pre_cmd_pad + 10] = SDSPI_START_BLOCK;
1328 spi_databuf[spi_pre_cmd_pad + 11] = sd->cmd53_wr_data & 0xFF;
1329 spi_databuf[spi_pre_cmd_pad + 12] = (sd->cmd53_wr_data & 0x0000FF00) >> 8;
1330 if (sd_crc) {
1331 dat_crc = sdspi_crc16(&spi_databuf[spi_pre_cmd_pad+11], 2);
1332 } else {
1333 dat_crc = 0x22AA;
1334 }
1335 spi_databuf[spi_pre_cmd_pad + 13] = (dat_crc >> 8) & 0xFF;
1336 spi_databuf[spi_pre_cmd_pad + 14] = (dat_crc & 0xFF);
1337 } else if (sd->data_xfer_count == 4) {
1338 spi_databuf[spi_pre_cmd_pad + 9] = SDSPI_IDLE_PAD;
1339 spi_databuf[spi_pre_cmd_pad + 10] = SDSPI_START_BLOCK;
1340 spi_databuf[spi_pre_cmd_pad + 11] = sd->cmd53_wr_data & 0xFF;
1341 spi_databuf[spi_pre_cmd_pad + 12] = (sd->cmd53_wr_data & 0x0000FF00) >> 8;
1342 spi_databuf[spi_pre_cmd_pad + 13] = (sd->cmd53_wr_data & 0x00FF0000) >> 16;
1343 spi_databuf[spi_pre_cmd_pad + 14] = (sd->cmd53_wr_data & 0xFF000000) >> 24;
1344 if (sd_crc) {
1345 dat_crc = sdspi_crc16(&spi_databuf[spi_pre_cmd_pad+11], 4);
1346 } else {
1347 dat_crc = 0x44AA;
1348 }
1349 spi_databuf[spi_pre_cmd_pad + 15] = (dat_crc >> 8) & 0xFF;
1350 spi_databuf[spi_pre_cmd_pad + 16] = (dat_crc & 0xFF);
1351 } else {
1352 printf("CMD53 Write: size %d unsupported\n", sd->data_xfer_count);
1353 }
1354 }
1355
1356 spi_sendrecv(sd, spi_databuf, spi_rspbuf, spi_datalen);
1357
1358 for (i = spi_pre_cmd_pad + SDSPI_COMMAND_LEN; i < spi_max_response_pad; i++) {
1359 if ((spi_rspbuf[i] & SDSPI_START_BIT_MASK) == 0) {
1360 break;
1361 }
1362 }
1363
1364 if (i == spi_max_response_pad) {
1365 sd_err(("%s: Did not get a response for CMD%d\n", __FUNCTION__, cmd));
1366 return ERROR;
1367 }
1368
1369 /* Extract the response. */
1370 sd->card_response = spi_rspbuf[i];
1371
1372 /* for CMD53 Read, find the start of the response data... */
1373 if ((cmd == SDIOH_CMD_53) && (GFIELD(cmd_arg, CMD52_RW_FLAG) == 0)) {
1374 for (; i < spi_max_response_pad; i++) {
1375 if (spi_rspbuf[i] == SDSPI_START_BLOCK) {
1376 break;
1377 }
1378 }
1379
1380 if (i == spi_max_response_pad) {
1381 printf("Did not get a start of data phase for CMD%d\n", cmd);
1382 max_errors++;
1383 sdspi_abort(sd, GFIELD(cmd_arg, CMD53_FUNCTION));
1384 }
1385 sd->card_rsp_data = spi_rspbuf[i+1];
1386 sd->card_rsp_data |= spi_rspbuf[i+2] << 8;
1387 sd->card_rsp_data |= spi_rspbuf[i+3] << 16;
1388 sd->card_rsp_data |= spi_rspbuf[i+4] << 24;
1389
1390 if (datalen != 0) {
1391 i++;
1392 for (j = 0; j < sd->data_xfer_count; j++) {
1393 ((uint8 *)data)[j] = spi_rspbuf[i+j];
1394 }
1395 if (sd_crc) {
1396 uint16 recv_crc;
1397
1398 recv_crc = spi_rspbuf[i+j] << 8 | spi_rspbuf[i+j+1];
1399 dat_crc = sdspi_crc16((uint8 *)data, datalen);
1400 if (dat_crc != recv_crc) {
1401 sd_err(("%s: Incorrect data CRC: expected 0x%04x, "
1402 "received 0x%04x\n",
1403 __FUNCTION__, dat_crc, recv_crc));
1404 }
1405 }
1406 }
1407 return SUCCESS;
1408 }
1409
1410 sd->card_rsp_data = spi_rspbuf[i+4];
1411 sd->card_rsp_data |= spi_rspbuf[i+3] << 8;
1412 sd->card_rsp_data |= spi_rspbuf[i+2] << 16;
1413 sd->card_rsp_data |= spi_rspbuf[i+1] << 24;
1414
1415 /* Display trace for byte read */
1416 if ((cmd == SDIOH_CMD_52) && (GFIELD(cmd_arg, CMD52_RW_FLAG) == 0)) {
1417 sd_trace(("%s: CMD52: Rd F:%d @0x%04x=%02x\n",
1418 __FUNCTION__,
1419 GFIELD(cmd_arg, CMD53_FUNCTION),
1420 GFIELD(cmd_arg, CMD53_REG_ADDR),
1421 sd->card_rsp_data >> 24));
1422 }
1423
1424 return SUCCESS;
1425 }
1426
1427 /*
1428 * On entry: if single-block or non-block, buffer size <= block size.
1429 * If multi-block, buffer size is unlimited.
1430 * Question is how to handle the left-overs in either single- or multi-block.
1431 * I think the caller should break the buffer up so this routine will always
1432 * use block size == buffer size to handle the end piece of the buffer
1433 */
1434
1435 static int
sdspi_card_buf(sdioh_info_t * sd,int rw,int func,bool fifo,uint32 addr,int nbytes,uint32 * data)1436 sdspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo, uint32 addr, int nbytes, uint32 *data)
1437 {
1438 int status;
1439 uint32 cmd_arg;
1440 uint32 rsp5;
1441 int num_blocks, blocksize;
1442 bool local_blockmode, local_dma;
1443 bool read = rw == SDIOH_READ ? 1 : 0;
1444
1445 ASSERT(nbytes);
1446
1447 cmd_arg = 0;
1448 sd_data(("%s: %s 53 func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1449 __FUNCTION__, read ? "Rd" : "Wr", func, fifo ? "FIXED" : "INCR",
1450 addr, nbytes, sd->r_cnt, sd->t_cnt));
1451
1452 if (read) sd->r_cnt++; else sd->t_cnt++;
1453
1454 local_blockmode = sd->sd_blockmode;
1455 local_dma = sd->sd_use_dma;
1456
1457 /* Don't bother with block mode on small xfers */
1458 if (nbytes < sd->client_block_size[func]) {
1459 sd_info(("setting local blockmode to false: nbytes (%d) != block_size (%d)\n",
1460 nbytes, sd->client_block_size[func]));
1461 local_blockmode = FALSE;
1462 local_dma = FALSE;
1463 }
1464
1465 if (local_blockmode) {
1466 blocksize = MIN(sd->client_block_size[func], nbytes);
1467 num_blocks = nbytes/blocksize;
1468 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, num_blocks);
1469 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 1);
1470 } else {
1471 num_blocks = 1;
1472 blocksize = nbytes;
1473 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, nbytes);
1474 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
1475 }
1476
1477 if (fifo)
1478 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 0);
1479 else
1480 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
1481
1482 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
1483 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, addr);
1484 if (read)
1485 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_READ);
1486 else
1487 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
1488
1489 sd->data_xfer_count = nbytes;
1490 if ((func == 2) && (fifo == 1)) {
1491 sd_data(("%s: %s 53 func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1492 __FUNCTION__, read ? "Rd" : "Wr", func, fifo ? "FIXED" : "INCR",
1493 addr, nbytes, sd->r_cnt, sd->t_cnt));
1494 }
1495
1496 /* sdspi_cmd_issue() returns with the command complete bit
1497 * in the ISR already cleared
1498 */
1499 if ((status = sdspi_cmd_issue(sd, local_dma,
1500 SDIOH_CMD_53, cmd_arg,
1501 data, nbytes)) != SUCCESS) {
1502 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__, (read ? "read" : "write")));
1503 return status;
1504 }
1505
1506 sdspi_cmd_getrsp(sd, &rsp5, 1);
1507
1508 if (rsp5 != 0x00) {
1509 sd_err(("%s: rsp5 flags = 0x%x, expecting 0x00\n",
1510 __FUNCTION__, rsp5));
1511 return ERROR;
1512 }
1513
1514 return SUCCESS;
1515 }
1516
1517 static int
set_client_block_size(sdioh_info_t * sd,int func,int block_size)1518 set_client_block_size(sdioh_info_t *sd, int func, int block_size)
1519 {
1520 int base;
1521 int err = 0;
1522
1523 sd_err(("%s: Setting block size %d, func %d\n", __FUNCTION__, block_size, func));
1524 sd->client_block_size[func] = block_size;
1525
1526 /* Set the block size in the SDIO Card register */
1527 base = func * SDIOD_FBR_SIZE;
1528 err = sdspi_card_regwrite(sd, 0, base + SDIOD_CCCR_BLKSIZE_0, 1, block_size & 0xff);
1529 if (!err) {
1530 err = sdspi_card_regwrite(sd, 0, base + SDIOD_CCCR_BLKSIZE_1, 1,
1531 (block_size >> 8) & 0xff);
1532 }
1533
1534 /*
1535 * Do not set the block size in the SDIO Host register; that
1536 * is func dependent and will get done on an individual
1537 * transaction basis.
1538 */
1539
1540 return (err ? BCME_SDIO_ERROR : 0);
1541 }
1542
1543 /* Reset and re-initialize the device */
1544 int
sdioh_sdio_reset(sdioh_info_t * si)1545 sdioh_sdio_reset(sdioh_info_t *si)
1546 {
1547 si->card_init_done = FALSE;
1548 return sdspi_client_init(si);
1549 }
1550
1551 #define CRC7_POLYNOM 0x09
1552 #define CRC7_CRCHIGHBIT 0x40
1553
sdspi_crc7(unsigned char * p,uint32 len)1554 static uint8 sdspi_crc7(unsigned char* p, uint32 len)
1555 {
1556 uint8 c, j, bit, crc = 0;
1557 uint32 i;
1558
1559 for (i = 0; i < len; i++) {
1560 c = *p++;
1561 for (j = 0x80; j; j >>= 1) {
1562 bit = crc & CRC7_CRCHIGHBIT;
1563 crc <<= 1;
1564 if (c & j) bit ^= CRC7_CRCHIGHBIT;
1565 if (bit) crc ^= CRC7_POLYNOM;
1566 }
1567 }
1568
1569 /* Convert the CRC7 to an 8-bit SD CRC */
1570 crc = (crc << 1) | 1;
1571
1572 return (crc);
1573 }
1574
1575 #define CRC16_POLYNOM 0x1021
1576 #define CRC16_CRCHIGHBIT 0x8000
1577
sdspi_crc16(unsigned char * p,uint32 len)1578 static uint16 sdspi_crc16(unsigned char* p, uint32 len)
1579 {
1580 uint32 i;
1581 uint16 j, c, bit;
1582 uint16 crc = 0;
1583
1584 for (i = 0; i < len; i++) {
1585 c = *p++;
1586 for (j = 0x80; j; j >>= 1) {
1587 bit = crc & CRC16_CRCHIGHBIT;
1588 crc <<= 1;
1589 if (c & j) bit ^= CRC16_CRCHIGHBIT;
1590 if (bit) crc ^= CRC16_POLYNOM;
1591 }
1592 }
1593
1594 return (crc);
1595 }
1596