1 /**************************************************************************** 2 **+-----------------------------------------------------------------------+** 3 **| |** 4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |** 5 **| All rights reserved. |** 6 **| |** 7 **| Redistribution and use in source and binary forms, with or without |** 8 **| modification, are permitted provided that the following conditions |** 9 **| are met: |** 10 **| |** 11 **| * Redistributions of source code must retain the above copyright |** 12 **| notice, this list of conditions and the following disclaimer. |** 13 **| * Redistributions in binary form must reproduce the above copyright |** 14 **| notice, this list of conditions and the following disclaimer in |** 15 **| the documentation and/or other materials provided with the |** 16 **| distribution. |** 17 **| * Neither the name Texas Instruments nor the names of its |** 18 **| contributors may be used to endorse or promote products derived |** 19 **| from this software without specific prior written permission. |** 20 **| |** 21 **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |** 22 **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |** 23 **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |** 24 **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |** 25 **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |** 26 **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |** 27 **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |** 28 **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |** 29 **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |** 30 **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |** 31 **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |** 32 **| |** 33 **+-----------------------------------------------------------------------+** 34 ****************************************************************************/ 35 36 /**************************************************************************** 37 * 38 * MODULE: whalHwRegs.h 39 * PURPOSE: Contains Wlan hardware registers defines/structures 40 * 41 ****************************************************************************/ 42 43 #ifndef _TNETW_COMMON_H 44 #define _TNETW_COMMON_H 45 46 #include "TnetwRegisters.h" 47 48 #define IS_MASK_ON( field, bitmask ) ( (bitmask) == ( (field) & (bitmask) ) ) 49 #define IS_MASK_OFF( field, bitmask ) ( ~(bitmask) == ( (field) | ~(bitmask) ) ) 50 51 #define IS_ANY_BIT_ON( field, bitmask ) ( (field) & (bitmask) ) 52 #define ARE_ALL_BITS_ON( field, bitmask ) IS_MASK_ON( field, bitmask ) 53 54 #define MASK_BITS_ON( field, bitmask ) ( (field) |= (bitmask) ) 55 #define MASK_BITS_OFF( field, bitmask ) ( (field) &= ~(bitmask) ) 56 57 #define MASK_BITS_TOGGLE( field, bitmask ) ( (field) ^= (bitmask) ) 58 59 #define ACX_PHI_CCA_THRSH_ENABLE_ENERGY_D 0x140A 60 #define ACX_PHI_CCA_THRSH_DISABLE_ENERGY_D 0xFFEF 61 62 /* 63 * Wlan hardware Registers. 64 */ 65 66 /*====================================================================== 67 Interrupt Registers 68 =======================================================================*/ 69 70 #define ACX_REG_INTERRUPT_TRIG ( INT_TRIG ) 71 72 #define ACX_REG_INTERRUPT_TRIG_H ( INT_TRIG_H ) 73 74 /*============================================= 75 Host Interrupt Mask Register - 32bit (RW) 76 ------------------------------------------ 77 Setting a bit in this register masks the 78 corresponding interrupt to the host. 79 0 - RX0 - Rx first dubble buffer Data Interrupt 80 1 - TXD - Tx Data Interrupt 81 2 - TXXFR - Tx Transfer Interrupt 82 3 - RX1 - Rx second dubble buffer Data Interrupt 83 4 - RXXFR - Rx Transfer Interrupt 84 5 - EVENT_A - Event Mailbox interrupt 85 6 - EVENT_B - Event Mailbox interrupt 86 7 - WNONHST - Wake On Host Interrupt 87 8 - TRACE_A - Debug Trace interrupt 88 9 - TRACE_B - Debug Trace interrupt 89 10 - CDCMP - Command Complete Interrupt 90 11 - 91 12 - 92 13 - 93 14 - ICOMP - Initialization Complete Interrupt 94 16 - SG SE - Soft Gemini - Sense enable interrupt 95 17 - SG SD - Soft Gemini - Sense disable interrupt 96 18 - - 97 19 - - 98 20 - - 99 21- - 100 Default: 0x0001 101 *==============================================*/ 102 #define ACX_REG_INTERRUPT_MASK ( HINT_MASK ) 103 104 /*============================================= 105 Host Interrupt Mask Set 16bit, (Write only) 106 ------------------------------------------ 107 Setting a bit in this register sets 108 the corresponding bin in ACX_HINT_MASK register 109 without effecting the mask 110 state of other bits (0 = no effect). 111 ==============================================*/ 112 #define ACX_HINT_MASK_SET_REG HINT_MASK_SET 113 114 /*============================================= 115 Host Interrupt Mask Clear 16bit,(Write only) 116 ------------------------------------------ 117 Setting a bit in this register clears 118 the corresponding bin in ACX_HINT_MASK register 119 without effecting the mask 120 state of other bits (0 = no effect). 121 =============================================*/ 122 #define ACX_HINT_MASK_CLR_REG HINT_MASK_CLR 123 124 /*============================================= 125 Host Interrupt Status Nondestructive Read 126 16bit,(Read only) 127 ------------------------------------------ 128 The host can read this register to determine 129 which interrupts are active. 130 Reading this register doesn't 131 effect its content. 132 =============================================*/ 133 #define ACX_REG_INTERRUPT_NO_CLEAR ( HINT_STS_ND ) 134 135 /*============================================= 136 Host Interrupt Status Clear on Read Register 137 16bit,(Read only) 138 ------------------------------------------ 139 The host can read this register to determine 140 which interrupts are active. 141 Reading this register clears it, 142 thus making all interrupts inactive. 143 ==============================================*/ 144 #define ACX_REG_INTERRUPT_CLEAR ( HINT_STS_CLR ) 145 146 /*============================================= 147 Host Interrupt Acknowledge Register 148 16bit,(Write only) 149 ------------------------------------------ 150 The host can set individual bits in this 151 register to clear (acknowledge) the corresp. 152 interrupt status bits in the HINT_STS_CLR and 153 HINT_STS_ND registers, thus making the 154 assotiated interrupt inactive. (0-no effect) 155 ==============================================*/ 156 #define ACX_REG_INTERRUPT_ACK ( HINT_ACK ) 157 158 159 /*=============================================== 160 Host Software Reset - 32bit RW 161 ------------------------------------------ 162 [31:1] Reserved 163 0 SOFT_RESET Soft Reset - When this bit is set, 164 it holds the Wlan hardware in a soft reset state. 165 This reset disables all MAC and baseband processor 166 clocks except the CardBus/PCI interface clock. 167 It also initializes all MAC state machines except 168 the host interface. It does not reload the 169 contents of the EEPROM. When this bit is cleared 170 (not self-clearing), the Wlan hardware 171 exits the software reset state. 172 ===============================================*/ 173 #define ACX_REG_SLV_SOFT_RESET ( SLV_SOFT_RESET ) 174 #define SLV_SOFT_RESET_BIT 0x00000001 175 176 /*=============================================== 177 EEPROM Burst Read Start - 32bit RW 178 ------------------------------------------ 179 [31:1] Reserved 180 0 ACX_EE_START - EEPROM Burst Read Start 0 181 Setting this bit starts a burst read from 182 the external EEPROM. 183 If this bit is set (after reset) before an EEPROM read/write, 184 the burst read starts at EEPROM address 0. 185 Otherwise, it starts at the address 186 following the address of the previous access. 187 TheWlan hardware hardware clears this bit automatically. 188 189 Default: 0x00000000 190 *================================================*/ 191 #define ACX_REG_EE_START ( EE_START ) 192 #define START_EEPROM_MGR 0x00000001 193 194 /*======================================================================= 195 Embedded ARM CPU Control 196 ========================================================================*/ 197 /*=============================================== 198 Halt eCPU - 32bit RW 199 ------------------------------------------ 200 0 HALT_ECPU Halt Embedded CPU - This bit is the 201 compliment of bit 1 (MDATA2) in the SOR_CFG register. 202 During a hardware reset, this bit holds 203 the inverse of MDATA2. 204 When downloading firmware from the host, 205 set this bit (pull down MDATA2). 206 The host clears this bit after downloading the firmware into 207 zero-wait-state SSRAM. 208 When loading firmware from Flash, clear this bit (pull up MDATA2) 209 so that the eCPU can run the bootloader code in Flash 210 HALT_ECPU eCPU State 211 -------------------- 212 1 halt eCPU 213 0 enable eCPU 214 ===============================================*/ 215 #define ACX_REG_ECPU_CONTROL ( ECPU_CTRL ) 216 217 218 /*======================================================================= 219 Command/Information Mailbox Pointers 220 ========================================================================*/ 221 222 /*=============================================== 223 Command Mailbox Pointer - 32bit RW 224 ------------------------------------------ 225 This register holds the start address of 226 the command mailbox located in the Wlan hardware memory. 227 The host must read this pointer after a reset to 228 find the location of the command mailbox. 229 The Wlan hardware initializes the command mailbox 230 pointer with the default address of the command mailbox. 231 The command mailbox pointer is not valid until after 232 the host receives the Init Complete interrupt from 233 the Wlan hardware. 234 ===============================================*/ 235 #define REG_COMMAND_MAILBOX_PTR ( SCR_PAD0 ) 236 237 /*=============================================== 238 Information Mailbox Pointer - 32bit RW 239 ------------------------------------------ 240 This register holds the start address of 241 the information mailbox located in the Wlan hardware memory. 242 The host must read this pointer after a reset to find 243 the location of the information mailbox. 244 The Wlan hardware initializes the information mailbox pointer 245 with the default address of the information mailbox. 246 The information mailbox pointer is not valid 247 until after the host receives the Init Complete interrupt from 248 the Wlan hardware. 249 ===============================================*/ 250 #define REG_EVENT_MAILBOX_PTR ( SCR_PAD1 ) 251 252 253 /*======================================================================= 254 Misc 255 ========================================================================*/ 256 257 258 #define REG_ENABLE_TX_RX ( ENABLE ) 259 /* 260 * Rx configuration (filter) information element 261 * --------------------------------------------- 262 */ 263 #define REG_RX_CONFIG ( RX_CFG ) 264 #define REG_RX_FILTER ( RX_FILTER_CFG ) 265 266 #define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 267 #define RX_CFG_PROMISCUOUS 0x0008 /* promiscuous - receives all valid frames */ 268 #define RX_CFG_BSSID 0x0020 /* receives frames from any BSSID */ 269 #define RX_CFG_MAC 0x0010 /* receives frames destined to any MAC address */ 270 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 271 #define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 272 #define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 273 #define RX_CFG_ENABLE_ANY_BSSID 0x0000 274 #define RX_CFG_DISABLE_BCAST 0x0200 /* discards all broadcast frames */ 275 #define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 276 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 277 #define RX_CFG_COPY_RX_STATUS 0x2000 278 #define RX_CFG_TSF 0x10000 279 280 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) 281 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) 282 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) 283 #define RX_CONFIG_OPTION_MY_DST_MY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) 284 285 #define RX_CONFIG_OPTION_FOR_SCAN ( RX_CFG_ENABLE_PHY_HEADER_PLCP | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) 286 #define RX_CONFIG_OPTION_FOR_MEASUREMENT ( RX_CFG_ENABLE_ANY_DEST_MAC ) 287 #define RX_CONFIG_OPTION_FOR_JOIN ( RX_CFG_ENABLE_ONLY_MY_BSSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) 288 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN ( RX_CFG_ENABLE_ONLY_MY_SSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) 289 290 #define RX_FILTER_OPTION_DEF (/*CFG_RX_PRSP_EN |*/ /*CFG_RX_PREQ_EN |*/ CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_BCN_EN | CFG_RX_AUTH_EN |CFG_RX_ASSOC_EN ) 291 #define RX_FILTER_OPTION_FILTER_ALL 0 292 #define RX_FILTER_OPTION_DEF_PRSP_BCN ( CFG_RX_PRSP_EN | CFG_RX_MGMT_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN ) 293 #define RX_FILTER_OPTION_JOIN ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN /*| CFG_RX_CTL_EN */| CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN) 294 295 296 /*=============================================== 297 Phy regs 298 ===============================================*/ 299 #define ACX_PHY_ADDR_REG SBB_ADDR 300 #define ACX_PHY_DATA_REG SBB_DATA 301 #define ACX_PHY_CTRL_REG SBB_CTL 302 #define ACX_PHY_REG_WR_MASK 0x00000001ul 303 #define ACX_PHY_REG_RD_MASK 0x00000002ul 304 305 306 /*=============================================== 307 EEPROM Read/Write Request 32bit RW 308 ------------------------------------------ 309 1 EE_READ - EEPROM Read Request 1 - Setting this bit 310 loads a single byte of data into the EE_DATA 311 register from the EEPROM location specified in 312 the EE_ADDR register. 313 The Wlan hardware hardware clears this bit automatically. 314 EE_DATA is valid when this bit is cleared. 315 0 EE_WRITE - EEPROM Write Request - Setting this bit 316 writes a single byte of data from the EE_DATA register into the 317 EEPROM location specified in the EE_ADDR register. 318 The Wlan hardware hardware clears this bit automatically. 319 *===============================================*/ 320 #define ACX_EE_CTL_REG EE_CTL 321 #define EE_WRITE 0x00000001ul 322 #define EE_READ 0x00000002ul 323 324 /*=============================================== 325 EEPROM Address - 32bit RW 326 ------------------------------------------ 327 This register specifies the address 328 within the EEPROM from/to which to read/write data. 329 ===============================================*/ 330 #define ACX_EE_ADDR_REG EE_ADDR 331 332 /*=============================================== 333 EEPROM Data - 32bit RW 334 ------------------------------------------ 335 This register either holds the read 8 bits of 336 data from the EEPROM or the write data 337 to be written to the EEPROM. 338 ===============================================*/ 339 #define ACX_EE_DATA_REG EE_DATA 340 341 /*=============================================== 342 EEPROM Base Address - 32bit RW 343 ------------------------------------------ 344 This register holds the upper nine bits 345 [23:15] of the 24-bit Wlan hardware memory 346 address for burst reads from EEPROM accesses. 347 The EEPROM provides the lower 15 bits of this address. 348 The MSB of the address from the EEPROM is ignored. 349 ===============================================*/ 350 #define ACX_EE_CFG EE_CFG 351 352 /*=============================================== 353 GPIO Output Values -32bit, RW 354 ------------------------------------------ 355 [31:16] Reserved 356 [15: 0] Specify the output values (at the output driver inputs) for 357 GPIO[15:0], respectively. 358 ===============================================*/ 359 #define ACX_GPIO_OUT_REG GPIO_OUT 360 #define ACX_MAX_GPIO_LINES 15 361 362 /*=============================================== 363 Contention window -32bit, RW 364 ------------------------------------------ 365 [31:26] Reserved 366 [25:16] Max (0x3ff) 367 [15:07] Reserved 368 [06:00] Current contention window value - default is 0x1F 369 ===============================================*/ 370 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 371 #define ACX_CONT_WIND_MIN_MASK 0x0000007f 372 #define ACX_CONT_WIND_MAX 0x03ff0000 373 374 /* 375 * Indirect slave register/memory registers 376 * ---------------------------------------- 377 */ 378 #define HW_SLAVE_REG_ADDR_REG 0x00000004 379 #define HW_SLAVE_REG_DATA_REG 0x00000008 380 #define HW_SLAVE_REG_CTRL_REG 0x0000000c 381 382 #define SLAVE_AUTO_INC 0x00010000 383 #define SLAVE_NO_AUTO_INC 0x00000000 384 #define SLAVE_HOST_LITTLE_ENDIAN 0x00000000 385 386 #define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR 387 #define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA 388 #define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL 389 #define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL 390 391 #define HW_FUNC_EVENT_INT_EN 0x8000 392 #define HW_FUNC_EVENT_MASK_REG 0x00000034 393 394 #define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP) 395 396 /*=============================================== 397 HI_CFG Interface Configuration Register Values 398 ------------------------------------------ 399 ===============================================*/ 400 #define HI_CFG_UART_ENABLE 0x00000004 401 #define HI_CFG_RST232_ENABLE 0x00000008 402 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010 403 #define HI_CFG_HOST_INT_ENABLE 0x00000020 404 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 405 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 406 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 407 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 408 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 409 410 /* 411 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile 412 * for platforms using active high interrupt level 413 */ 414 #ifdef USE_ACTIVE_HIGH 415 #define HI_CFG_DEF_VAL \ 416 HI_CFG_UART_ENABLE | \ 417 HI_CFG_RST232_ENABLE | \ 418 HI_CFG_CLOCK_REQ_SELECT | \ 419 HI_CFG_HOST_INT_ENABLE 420 #else 421 #define HI_CFG_DEF_VAL \ 422 HI_CFG_UART_ENABLE | \ 423 HI_CFG_RST232_ENABLE | \ 424 HI_CFG_CLOCK_REQ_SELECT | \ 425 HI_CFG_HOST_INT_ENABLE | \ 426 HI_CFG_HOST_INT_ACTIVE_LOW 427 #endif 428 429 #endif /* _TNETW_COMMON_H */ 430 431