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Searched refs:r7 (Results 1 – 20 of 20) sorted by relevance

/dalvik/vm/arch/arm/
DCallEABI.S184 @ Stick argv in r7 and advance it past the argv values that will be
327 @ Set up to copy from r7 to r8. We copy from the second arg to the
331 mov r7, r9 @ r7<- argv
334 @ We need to copy words from [r7] to [r8]. We walk forward through
338 add r7, r7, #8 @ r7<- r7+8 (assume argv 0/1 in r2/r3)
350 subeq r7, #4 @ r7<- r7-4 (take it back - pad word)
369 ldr ip, [r7], #4
378 ldr ip, [r7], #4
380 ldr r2, [r7], #4
/dalvik/vm/compiler/template/armv5te/
DTEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S31 ldr r7, [r3, #offClassObject_vtable] @ r7 <- this->class->vtable
Dheader.S77 #define rINST r7
DTEMPLATE_INVOKE_METHOD_CHAIN.S9 ldrh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
15 sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
DTEMPLATE_INVOKE_METHOD_NO_OPT.S7 ldrh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
13 sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
DTEMPLATE_INVOKE_METHOD_NATIVE.S2 ldrh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
7 sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
/dalvik/vm/compiler/codegen/arm/armv5te/
DArchVariant.c71 loadConstant(cUnit, r7, (int) templatePtr); in genDispatchToHandler()
72 newLIR1(cUnit, THUMB_BLX_R, r7); in genDispatchToHandler()
/dalvik/vm/arch/sh/
DCallSH4ABI.S65 ## r12 ... status of r6, and r7
67 ## bit 1 << 1 : if r7 is available, it contains 1.
127 mov.l @r3+, r7 /* put one arg in r7 */
147 mov.l @r3+, r7
/dalvik/vm/compiler/template/out/
DCompilerTemplateAsm-armv7-a.S84 #define rINST r7
DCompilerTemplateAsm-armv5te-vfp.S84 #define rINST r7
DCompilerTemplateAsm-armv5te.S84 #define rINST r7
/dalvik/vm/compiler/codegen/arm/armv5te-vfp/
DArchVariant.c71 loadConstant(cUnit, r7, (int) templatePtr); in genDispatchToHandler()
72 newLIR1(cUnit, THUMB_BLX_R, r7); in genDispatchToHandler()
/dalvik/vm/compiler/codegen/arm/armv7-a/
DArchVariant.c74 loadConstant(cUnit, r7, (int) templatePtr); in genDispatchToHandler()
75 newLIR1(cUnit, THUMB_BLX_R, r7); in genDispatchToHandler()
/dalvik/vm/mterp/armv5te/
Dheader.S71 #define rINST r7
/dalvik/vm/compiler/codegen/arm/
DCodegen.c1056 newLIR2(cUnit, THUMB_MOV_RR, r7, rFP); in genProcessArgsNoRange()
1057 newLIR2(cUnit, THUMB_SUB_RI8, r7, in genProcessArgsNoRange()
1064 newLIR2(cUnit, THUMB_STMIA, r7, regMask); in genProcessArgsNoRange()
1090 newLIR2(cUnit, THUMB_MOV_RR, r7, rFP); in genProcessArgsRange()
1091 newLIR2(cUnit, THUMB_SUB_RI8, r7, in genProcessArgsRange()
1094 loadConstant(cUnit, r7, sizeof(StackSaveArea) + (numArgs << 2)); in genProcessArgsRange()
1095 newLIR3(cUnit, THUMB_SUB_RRR, r7, rFP, r7); in genProcessArgsRange()
1119 newLIR2(cUnit, THUMB_STMIA, r7, regMask); in genProcessArgsRange()
1129 newLIR2(cUnit, THUMB_STMIA, r7, regMask); in genProcessArgsRange()
1141 newLIR2(cUnit, THUMB_STMIA, r7, regMask); in genProcessArgsRange()
[all …]
DArmLIR.h78 r7 = 7, enumerator
/dalvik/vm/mterp/out/
DInterpAsm-armv7-a.S78 #define rINST r7
DInterpAsm-armv5te-vfp.S78 #define rINST r7
DInterpAsm-armv4t.S78 #define rINST r7
DInterpAsm-armv5te.S78 #define rINST r7