Searched refs:CPSR_M (Results 1 – 3 of 3) sorted by relevance
232 #define CPSR_M (0x1f) macro417 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; in cpu_mmu_index()444 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) in cpu_get_tb_cpu_state()
374 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { in cpsr_write()375 switch_mode(env, val & CPSR_M); in cpsr_write()617 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()813 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { in do_interrupt()829 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { in do_interrupt()876 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; in do_interrupt()
5858 if (op1 == (env->uncached_cpsr & CPSR_M)) { in disas_arm_insn()5891 if (op1 == (env->uncached_cpsr & CPSR_M)) { in disas_arm_insn()5982 mask |= CPSR_M; in disas_arm_insn()7356 if (op == (env->uncached_cpsr & CPSR_M)) { in disas_thumb2_insn()7377 if (op == (env->uncached_cpsr & CPSR_M)) { in disas_thumb2_insn()