72 	outw(RX_DISABLE, BASE + EP_COMMAND);  in t509_reset()
73 	outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);  in t509_reset()
76 	outw(TX_DISABLE, BASE + EP_COMMAND);  in t509_reset()
77 	outw(STOP_TRANSCEIVER, BASE + EP_COMMAND);  in t509_reset()
79 	outw(RX_RESET, BASE + EP_COMMAND);  in t509_reset()
80 	outw(TX_RESET, BASE + EP_COMMAND);  in t509_reset()
81 	outw(C_INTR_LATCH, BASE + EP_COMMAND);  in t509_reset()
82 	outw(SET_RD_0_MASK, BASE + EP_COMMAND);  in t509_reset()
83 	outw(SET_INTR_MASK, BASE + EP_COMMAND);  in t509_reset()
84 	outw(SET_RX_FILTER, BASE + EP_COMMAND);  in t509_reset()
109 	outw(RX_RESET, BASE + EP_COMMAND);  in t509_reset()
110 	outw(TX_RESET, BASE + EP_COMMAND);  in t509_reset()
118 	outw(ACK_INTR | 0xff, BASE + EP_COMMAND);  in t509_reset()
120 	outw(SET_RD_0_MASK | S_5_INTS, BASE + EP_COMMAND);  in t509_reset()
122 	outw(SET_INTR_MASK, BASE + EP_COMMAND);  in t509_reset()
124 	outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + EP_COMMAND);  in t509_reset()
128 		outw(START_TRANSCEIVER, BASE + EP_COMMAND);  in t509_reset()
140 	outw(RX_ENABLE, BASE + EP_COMMAND);  in t509_reset()
141 	outw(TX_ENABLE, BASE + EP_COMMAND);  in t509_reset()
144 	outw(SET_RX_EARLY_THRESH | ETH_ZLEN, BASE + EP_COMMAND);  in t509_reset()
145 	outw(SET_TX_START_THRESH | 16, BASE + EP_COMMAND);  in t509_reset()
187 			outw(TX_RESET, BASE + EP_COMMAND);  in t509_transmit()
188 			outw(TX_ENABLE, BASE + EP_COMMAND);  in t509_transmit()
235 		outw(ACK_INTR| (cst & S_5_INTS), BASE + EP_COMMAND);  in t509_poll()
236 		outw(C_INTR_LATCH, BASE + EP_COMMAND);  in t509_poll()
247 		outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);  in t509_poll()
288 	outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);  in t509_poll()