36     gic_state gic;  member
94     gic_set_pending_private(&s->gic, 0, irq);  in armv7m_nvic_set_pending()
103     irq = gic_acknowledge_irq(&s->gic, 0);  in armv7m_nvic_acknowledge_irq()
116     gic_complete_irq(&s->gic, 0, irq);  in armv7m_nvic_complete_irq()
156         val = s->gic.running_irq[0];  in nvic_readl()
163         if (s->gic.running_irq[0] == 1023  in nvic_readl()
164                 || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {  in nvic_readl()
168         if (s->gic.current_pending[0] != 1023)  in nvic_readl()
169             val |= (s->gic.current_pending[0] << 12);  in nvic_readl()
172             if (s->gic.irq_state[irq].pending) {  in nvic_readl()
178         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)  in nvic_readl()
181         if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)  in nvic_readl()
184         if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)  in nvic_readl()
200         val = s->gic.priority1[irq++][0];  in nvic_readl()
201         val = s->gic.priority1[irq++][0] << 8;  in nvic_readl()
202         val = s->gic.priority1[irq++][0] << 16;  in nvic_readl()
203         val = s->gic.priority1[irq][0] << 24;  in nvic_readl()
207         if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);  in nvic_readl()
208         if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);  in nvic_readl()
209         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);  in nvic_readl()
210         if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);  in nvic_readl()
211         if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);  in nvic_readl()
212         if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);  in nvic_readl()
213         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);  in nvic_readl()
214         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);  in nvic_readl()
215         if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);  in nvic_readl()
216         if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);  in nvic_readl()
217         if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);  in nvic_readl()
218         if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);  in nvic_readl()
219         if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);  in nvic_readl()
220         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);  in nvic_readl()
310             s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;  in nvic_writel()
311             gic_update(&s->gic);  in nvic_writel()
316             s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;  in nvic_writel()
317             gic_update(&s->gic);  in nvic_writel()
341             s->gic.priority1[irq++][0] = value & 0xff;  in nvic_writel()
342             s->gic.priority1[irq++][0] = (value >> 8) & 0xff;  in nvic_writel()
343             s->gic.priority1[irq++][0] = (value >> 16) & 0xff;  in nvic_writel()
344             s->gic.priority1[irq][0] = (value >> 24) & 0xff;  in nvic_writel()
345             gic_update(&s->gic);  in nvic_writel()
351         s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;  in nvic_writel()
352         s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;  in nvic_writel()
353         s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;  in nvic_writel()
397     gic_init(&s->gic);  in armv7m_nvic_init()
398     cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);  in armv7m_nvic_init()