Lines Matching refs:dma_controllers
60 } dma_controllers[2]; variable
304 return dma_controllers[nchan > 3].regs[nchan & 3].mode; in DMA_get_channel_mode()
314 dma_controllers[ncont].status |= 1 << (ichan + 4); in DMA_hold_DREQ()
325 dma_controllers[ncont].status &= ~(1 << (ichan + 4)); in DMA_release_DREQ()
332 struct dma_regs *r = &dma_controllers[ncont].regs[ichan]; in channel_run()
347 r = dma_controllers[ncont].regs + ichan; in channel_run()
362 d = dma_controllers; in DMA_run()
396 r = dma_controllers[ncont].regs + ichan; in DMA_register_channel()
403 struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; in DMA_read_memory()
425 struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; in DMA_write_memory()
562 dma_init2(&dma_controllers[0], 0x00, 0, 0x80, in DMA_init()
564 dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, in DMA_init()
566 register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); in DMA_init()
567 register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); in DMA_init()