58     int dshift;  member
138     r->now[ADDR] = r->base[ADDR] << d->dshift;  in init_chan()
157     iport = (nport >> d->dshift) & 0x0f;  in read_chan()
165         val = (r->base[COUNT] << d->dshift) - r->now[COUNT];  in read_chan()
170     return (val >> (d->dshift + (ff << 3))) & 0xff;  in read_chan()
179     iport = (nport >> d->dshift) & 0x0f;  in write_chan()
196     iport = (nport >> d->dshift) & 0x0f;  in write_cont()
284     iport = (nport >> d->dshift) & 0x0f;  in read_cont()
456     write_cont (d, (0x0d << d->dshift), 0);  in dma_reset()
467 static void dma_init2(struct dma_cont *d, int base, int dshift,  in dma_init2()  argument
473     d->dshift = dshift;  in dma_init2()
475         register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);  in dma_init2()
476         register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);  in dma_init2()
491         register_ioport_write (base + ((i + 8) << dshift), 1, 1,  in dma_init2()
493         register_ioport_read (base + ((i + 8) << dshift), 1, 1,  in dma_init2()
512     qemu_put_be32 (f, d->dshift);  in dma_save()
540     d->dshift=qemu_get_be32 (f);  in dma_load()