1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "tcg.h"
25
26 int gen_new_label(void);
27
tcg_gen_op1_i32(int opc,TCGv_i32 arg1)28 static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
29 {
30 *gen_opc_ptr++ = opc;
31 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
32 }
33
tcg_gen_op1_i64(int opc,TCGv_i64 arg1)34 static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
35 {
36 *gen_opc_ptr++ = opc;
37 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
38 }
39
tcg_gen_op1i(int opc,TCGArg arg1)40 static inline void tcg_gen_op1i(int opc, TCGArg arg1)
41 {
42 *gen_opc_ptr++ = opc;
43 *gen_opparam_ptr++ = arg1;
44 }
45
tcg_gen_op2_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2)46 static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
47 {
48 *gen_opc_ptr++ = opc;
49 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
50 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
51 }
52
tcg_gen_op2_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2)53 static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
54 {
55 *gen_opc_ptr++ = opc;
56 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
57 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
58 }
59
tcg_gen_op2i_i32(int opc,TCGv_i32 arg1,TCGArg arg2)60 static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
61 {
62 *gen_opc_ptr++ = opc;
63 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
64 *gen_opparam_ptr++ = arg2;
65 }
66
tcg_gen_op2i_i64(int opc,TCGv_i64 arg1,TCGArg arg2)67 static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
68 {
69 *gen_opc_ptr++ = opc;
70 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
71 *gen_opparam_ptr++ = arg2;
72 }
73
tcg_gen_op2ii(int opc,TCGArg arg1,TCGArg arg2)74 static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
75 {
76 *gen_opc_ptr++ = opc;
77 *gen_opparam_ptr++ = arg1;
78 *gen_opparam_ptr++ = arg2;
79 }
80
tcg_gen_op3_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3)81 static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
82 TCGv_i32 arg3)
83 {
84 *gen_opc_ptr++ = opc;
85 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
86 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
87 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
88 }
89
tcg_gen_op3_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3)90 static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
91 TCGv_i64 arg3)
92 {
93 *gen_opc_ptr++ = opc;
94 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
95 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
96 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
97 }
98
tcg_gen_op3i_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGArg arg3)99 static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
100 TCGArg arg3)
101 {
102 *gen_opc_ptr++ = opc;
103 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
104 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
105 *gen_opparam_ptr++ = arg3;
106 }
107
tcg_gen_op3i_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGArg arg3)108 static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
109 TCGArg arg3)
110 {
111 *gen_opc_ptr++ = opc;
112 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
113 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
114 *gen_opparam_ptr++ = arg3;
115 }
116
tcg_gen_ldst_op_i32(int opc,TCGv_i32 val,TCGv_ptr base,TCGArg offset)117 static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
118 TCGArg offset)
119 {
120 *gen_opc_ptr++ = opc;
121 *gen_opparam_ptr++ = GET_TCGV_I32(val);
122 *gen_opparam_ptr++ = GET_TCGV_PTR(base);
123 *gen_opparam_ptr++ = offset;
124 }
125
tcg_gen_ldst_op_i64(int opc,TCGv_i64 val,TCGv_ptr base,TCGArg offset)126 static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
127 TCGArg offset)
128 {
129 *gen_opc_ptr++ = opc;
130 *gen_opparam_ptr++ = GET_TCGV_I64(val);
131 *gen_opparam_ptr++ = GET_TCGV_PTR(base);
132 *gen_opparam_ptr++ = offset;
133 }
134
tcg_gen_qemu_ldst_op_i64_i32(int opc,TCGv_i64 val,TCGv_i32 addr,TCGArg mem_index)135 static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
136 TCGArg mem_index)
137 {
138 *gen_opc_ptr++ = opc;
139 *gen_opparam_ptr++ = GET_TCGV_I64(val);
140 *gen_opparam_ptr++ = GET_TCGV_I32(addr);
141 *gen_opparam_ptr++ = mem_index;
142 }
143
tcg_gen_qemu_ldst_op_i64_i64(int opc,TCGv_i64 val,TCGv_i64 addr,TCGArg mem_index)144 static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
145 TCGArg mem_index)
146 {
147 *gen_opc_ptr++ = opc;
148 *gen_opparam_ptr++ = GET_TCGV_I64(val);
149 *gen_opparam_ptr++ = GET_TCGV_I64(addr);
150 *gen_opparam_ptr++ = mem_index;
151 }
152
tcg_gen_op4_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGv_i32 arg4)153 static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
154 TCGv_i32 arg3, TCGv_i32 arg4)
155 {
156 *gen_opc_ptr++ = opc;
157 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
158 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
159 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
160 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
161 }
162
tcg_gen_op4_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGv_i64 arg4)163 static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
164 TCGv_i64 arg3, TCGv_i64 arg4)
165 {
166 *gen_opc_ptr++ = opc;
167 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
168 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
169 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
170 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
171 }
172
tcg_gen_op4i_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGArg arg4)173 static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
174 TCGv_i32 arg3, TCGArg arg4)
175 {
176 *gen_opc_ptr++ = opc;
177 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
178 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
179 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
180 *gen_opparam_ptr++ = arg4;
181 }
182
tcg_gen_op4i_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGArg arg4)183 static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
184 TCGv_i64 arg3, TCGArg arg4)
185 {
186 *gen_opc_ptr++ = opc;
187 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
188 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
189 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
190 *gen_opparam_ptr++ = arg4;
191 }
192
tcg_gen_op4ii_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGArg arg3,TCGArg arg4)193 static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
194 TCGArg arg3, TCGArg arg4)
195 {
196 *gen_opc_ptr++ = opc;
197 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
198 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
199 *gen_opparam_ptr++ = arg3;
200 *gen_opparam_ptr++ = arg4;
201 }
202
tcg_gen_op4ii_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGArg arg3,TCGArg arg4)203 static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
204 TCGArg arg3, TCGArg arg4)
205 {
206 *gen_opc_ptr++ = opc;
207 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
208 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
209 *gen_opparam_ptr++ = arg3;
210 *gen_opparam_ptr++ = arg4;
211 }
212
tcg_gen_op5_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGv_i32 arg4,TCGv_i32 arg5)213 static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
214 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
215 {
216 *gen_opc_ptr++ = opc;
217 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
218 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
219 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
220 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
221 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
222 }
223
tcg_gen_op5_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGv_i64 arg4,TCGv_i64 arg5)224 static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
225 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
226 {
227 *gen_opc_ptr++ = opc;
228 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
229 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
230 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
231 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
232 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
233 }
234
tcg_gen_op5i_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGv_i32 arg4,TCGArg arg5)235 static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
236 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
237 {
238 *gen_opc_ptr++ = opc;
239 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
240 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
241 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
242 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
243 *gen_opparam_ptr++ = arg5;
244 }
245
tcg_gen_op5i_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGv_i64 arg4,TCGArg arg5)246 static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
247 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
248 {
249 *gen_opc_ptr++ = opc;
250 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
251 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
252 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
253 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
254 *gen_opparam_ptr++ = arg5;
255 }
256
tcg_gen_op6_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGv_i32 arg4,TCGv_i32 arg5,TCGv_i32 arg6)257 static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
258 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
259 TCGv_i32 arg6)
260 {
261 *gen_opc_ptr++ = opc;
262 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
263 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
264 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
265 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
266 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
267 *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
268 }
269
tcg_gen_op6_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGv_i64 arg4,TCGv_i64 arg5,TCGv_i64 arg6)270 static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
271 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
272 TCGv_i64 arg6)
273 {
274 *gen_opc_ptr++ = opc;
275 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
276 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
277 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
278 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
279 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
280 *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
281 }
282
tcg_gen_op6i_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGv_i32 arg4,TCGv_i32 arg5,TCGArg arg6)283 static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
284 TCGv_i32 arg3, TCGv_i32 arg4,
285 TCGv_i32 arg5, TCGArg arg6)
286 {
287 *gen_opc_ptr++ = opc;
288 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
289 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
290 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
291 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
292 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
293 *gen_opparam_ptr++ = arg6;
294 }
295
tcg_gen_op6i_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGv_i64 arg4,TCGv_i64 arg5,TCGArg arg6)296 static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
297 TCGv_i64 arg3, TCGv_i64 arg4,
298 TCGv_i64 arg5, TCGArg arg6)
299 {
300 *gen_opc_ptr++ = opc;
301 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
302 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
303 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
304 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
305 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
306 *gen_opparam_ptr++ = arg6;
307 }
308
tcg_gen_op6ii_i32(int opc,TCGv_i32 arg1,TCGv_i32 arg2,TCGv_i32 arg3,TCGv_i32 arg4,TCGArg arg5,TCGArg arg6)309 static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
310 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
311 TCGArg arg6)
312 {
313 *gen_opc_ptr++ = opc;
314 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
315 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
316 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
317 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
318 *gen_opparam_ptr++ = arg5;
319 *gen_opparam_ptr++ = arg6;
320 }
321
tcg_gen_op6ii_i64(int opc,TCGv_i64 arg1,TCGv_i64 arg2,TCGv_i64 arg3,TCGv_i64 arg4,TCGArg arg5,TCGArg arg6)322 static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
323 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
324 TCGArg arg6)
325 {
326 *gen_opc_ptr++ = opc;
327 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
328 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
329 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
330 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
331 *gen_opparam_ptr++ = arg5;
332 *gen_opparam_ptr++ = arg6;
333 }
334
gen_set_label(int n)335 static inline void gen_set_label(int n)
336 {
337 tcg_gen_op1i(INDEX_op_set_label, n);
338 }
339
tcg_gen_br(int label)340 static inline void tcg_gen_br(int label)
341 {
342 tcg_gen_op1i(INDEX_op_br, label);
343 }
344
tcg_gen_mov_i32(TCGv_i32 ret,TCGv_i32 arg)345 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
346 {
347 if (!TCGV_EQUAL_I32(ret, arg))
348 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
349 }
350
tcg_gen_movi_i32(TCGv_i32 ret,int32_t arg)351 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
352 {
353 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
354 }
355
356 /* helper calls */
tcg_gen_helperN(void * func,int flags,int sizemask,TCGArg ret,int nargs,TCGArg * args)357 static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
358 TCGArg ret, int nargs, TCGArg *args)
359 {
360 TCGv_ptr fn;
361 fn = tcg_const_ptr((tcg_target_long)func);
362 tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
363 nargs, args);
364 tcg_temp_free_ptr(fn);
365 }
366
367 /* FIXME: Should this be pure? */
tcg_gen_helper64(void * func,TCGv_i64 ret,TCGv_i64 a,TCGv_i64 b)368 static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
369 TCGv_i64 a, TCGv_i64 b)
370 {
371 TCGv_ptr fn;
372 TCGArg args[2];
373 fn = tcg_const_ptr((tcg_target_long)func);
374 args[0] = GET_TCGV_I64(a);
375 args[1] = GET_TCGV_I64(b);
376 tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
377 tcg_temp_free_ptr(fn);
378 }
379
380 /* 32 bit ops */
381
tcg_gen_ld8u_i32(TCGv_i32 ret,TCGv_ptr arg2,tcg_target_long offset)382 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
383 {
384 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
385 }
386
tcg_gen_ld8s_i32(TCGv_i32 ret,TCGv_ptr arg2,tcg_target_long offset)387 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
388 {
389 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
390 }
391
tcg_gen_ld16u_i32(TCGv_i32 ret,TCGv_ptr arg2,tcg_target_long offset)392 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
393 {
394 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
395 }
396
tcg_gen_ld16s_i32(TCGv_i32 ret,TCGv_ptr arg2,tcg_target_long offset)397 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
398 {
399 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
400 }
401
tcg_gen_ld_i32(TCGv_i32 ret,TCGv_ptr arg2,tcg_target_long offset)402 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
403 {
404 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
405 }
406
tcg_gen_st8_i32(TCGv_i32 arg1,TCGv_ptr arg2,tcg_target_long offset)407 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
408 {
409 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
410 }
411
tcg_gen_st16_i32(TCGv_i32 arg1,TCGv_ptr arg2,tcg_target_long offset)412 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
413 {
414 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
415 }
416
tcg_gen_st_i32(TCGv_i32 arg1,TCGv_ptr arg2,tcg_target_long offset)417 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
418 {
419 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
420 }
421
tcg_gen_add_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)422 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
423 {
424 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
425 }
426
tcg_gen_addi_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)427 static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
428 {
429 /* some cases can be optimized here */
430 if (arg2 == 0) {
431 tcg_gen_mov_i32(ret, arg1);
432 } else {
433 TCGv_i32 t0 = tcg_const_i32(arg2);
434 tcg_gen_add_i32(ret, arg1, t0);
435 tcg_temp_free_i32(t0);
436 }
437 }
438
tcg_gen_sub_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)439 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
440 {
441 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
442 }
443
tcg_gen_subfi_i32(TCGv_i32 ret,int32_t arg1,TCGv_i32 arg2)444 static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
445 {
446 TCGv_i32 t0 = tcg_const_i32(arg1);
447 tcg_gen_sub_i32(ret, t0, arg2);
448 tcg_temp_free_i32(t0);
449 }
450
tcg_gen_subi_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)451 static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
452 {
453 /* some cases can be optimized here */
454 if (arg2 == 0) {
455 tcg_gen_mov_i32(ret, arg1);
456 } else {
457 TCGv_i32 t0 = tcg_const_i32(arg2);
458 tcg_gen_sub_i32(ret, arg1, t0);
459 tcg_temp_free_i32(t0);
460 }
461 }
462
tcg_gen_and_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)463 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
464 {
465 if (TCGV_EQUAL_I32(arg1, arg2)) {
466 tcg_gen_mov_i32(ret, arg1);
467 } else {
468 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
469 }
470 }
471
tcg_gen_andi_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)472 static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
473 {
474 /* some cases can be optimized here */
475 if (arg2 == 0) {
476 tcg_gen_movi_i32(ret, 0);
477 } else if (arg2 == 0xffffffff) {
478 tcg_gen_mov_i32(ret, arg1);
479 } else {
480 TCGv_i32 t0 = tcg_const_i32(arg2);
481 tcg_gen_and_i32(ret, arg1, t0);
482 tcg_temp_free_i32(t0);
483 }
484 }
485
tcg_gen_or_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)486 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
487 {
488 if (TCGV_EQUAL_I32(arg1, arg2)) {
489 tcg_gen_mov_i32(ret, arg1);
490 } else {
491 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
492 }
493 }
494
tcg_gen_ori_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)495 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
496 {
497 /* some cases can be optimized here */
498 if (arg2 == 0xffffffff) {
499 tcg_gen_movi_i32(ret, 0xffffffff);
500 } else if (arg2 == 0) {
501 tcg_gen_mov_i32(ret, arg1);
502 } else {
503 TCGv_i32 t0 = tcg_const_i32(arg2);
504 tcg_gen_or_i32(ret, arg1, t0);
505 tcg_temp_free_i32(t0);
506 }
507 }
508
tcg_gen_xor_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)509 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
510 {
511 if (TCGV_EQUAL_I32(arg1, arg2)) {
512 tcg_gen_movi_i32(ret, 0);
513 } else {
514 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
515 }
516 }
517
tcg_gen_xori_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)518 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
519 {
520 /* some cases can be optimized here */
521 if (arg2 == 0) {
522 tcg_gen_mov_i32(ret, arg1);
523 } else {
524 TCGv_i32 t0 = tcg_const_i32(arg2);
525 tcg_gen_xor_i32(ret, arg1, t0);
526 tcg_temp_free_i32(t0);
527 }
528 }
529
tcg_gen_shl_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)530 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
531 {
532 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
533 }
534
tcg_gen_shli_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)535 static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
536 {
537 if (arg2 == 0) {
538 tcg_gen_mov_i32(ret, arg1);
539 } else {
540 TCGv_i32 t0 = tcg_const_i32(arg2);
541 tcg_gen_shl_i32(ret, arg1, t0);
542 tcg_temp_free_i32(t0);
543 }
544 }
545
tcg_gen_shr_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)546 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
547 {
548 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
549 }
550
tcg_gen_shri_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)551 static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
552 {
553 if (arg2 == 0) {
554 tcg_gen_mov_i32(ret, arg1);
555 } else {
556 TCGv_i32 t0 = tcg_const_i32(arg2);
557 tcg_gen_shr_i32(ret, arg1, t0);
558 tcg_temp_free_i32(t0);
559 }
560 }
561
tcg_gen_sar_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)562 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
563 {
564 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
565 }
566
tcg_gen_sari_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)567 static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
568 {
569 if (arg2 == 0) {
570 tcg_gen_mov_i32(ret, arg1);
571 } else {
572 TCGv_i32 t0 = tcg_const_i32(arg2);
573 tcg_gen_sar_i32(ret, arg1, t0);
574 tcg_temp_free_i32(t0);
575 }
576 }
577
tcg_gen_brcond_i32(int cond,TCGv_i32 arg1,TCGv_i32 arg2,int label_index)578 static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
579 int label_index)
580 {
581 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
582 }
583
tcg_gen_brcondi_i32(int cond,TCGv_i32 arg1,int32_t arg2,int label_index)584 static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
585 int label_index)
586 {
587 TCGv_i32 t0 = tcg_const_i32(arg2);
588 tcg_gen_brcond_i32(cond, arg1, t0, label_index);
589 tcg_temp_free_i32(t0);
590 }
591
tcg_gen_setcond_i32(int cond,TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)592 static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret,
593 TCGv_i32 arg1, TCGv_i32 arg2)
594 {
595 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
596 }
597
tcg_gen_setcondi_i32(int cond,TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)598 static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1,
599 int32_t arg2)
600 {
601 TCGv_i32 t0 = tcg_const_i32(arg2);
602 tcg_gen_setcond_i32(cond, ret, arg1, t0);
603 tcg_temp_free_i32(t0);
604 }
605
tcg_gen_mul_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)606 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
607 {
608 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
609 }
610
tcg_gen_muli_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)611 static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
612 {
613 TCGv_i32 t0 = tcg_const_i32(arg2);
614 tcg_gen_mul_i32(ret, arg1, t0);
615 tcg_temp_free_i32(t0);
616 }
617
618 #ifdef TCG_TARGET_HAS_div_i32
tcg_gen_div_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)619 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
620 {
621 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
622 }
623
tcg_gen_rem_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)624 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
625 {
626 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
627 }
628
tcg_gen_divu_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)629 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
630 {
631 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
632 }
633
tcg_gen_remu_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)634 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
635 {
636 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
637 }
638 #else
tcg_gen_div_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)639 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
640 {
641 TCGv_i32 t0;
642 t0 = tcg_temp_new_i32();
643 tcg_gen_sari_i32(t0, arg1, 31);
644 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
645 tcg_temp_free_i32(t0);
646 }
647
tcg_gen_rem_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)648 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
649 {
650 TCGv_i32 t0;
651 t0 = tcg_temp_new_i32();
652 tcg_gen_sari_i32(t0, arg1, 31);
653 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
654 tcg_temp_free_i32(t0);
655 }
656
tcg_gen_divu_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)657 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
658 {
659 TCGv_i32 t0;
660 t0 = tcg_temp_new_i32();
661 tcg_gen_movi_i32(t0, 0);
662 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
663 tcg_temp_free_i32(t0);
664 }
665
tcg_gen_remu_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)666 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
667 {
668 TCGv_i32 t0;
669 t0 = tcg_temp_new_i32();
670 tcg_gen_movi_i32(t0, 0);
671 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
672 tcg_temp_free_i32(t0);
673 }
674 #endif
675
676 #if TCG_TARGET_REG_BITS == 32
677
tcg_gen_mov_i64(TCGv_i64 ret,TCGv_i64 arg)678 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
679 {
680 if (!TCGV_EQUAL_I64(ret, arg)) {
681 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
682 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
683 }
684 }
685
tcg_gen_movi_i64(TCGv_i64 ret,int64_t arg)686 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
687 {
688 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
689 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
690 }
691
tcg_gen_ld8u_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)692 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
693 tcg_target_long offset)
694 {
695 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
696 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
697 }
698
tcg_gen_ld8s_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)699 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
700 tcg_target_long offset)
701 {
702 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
703 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
704 }
705
tcg_gen_ld16u_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)706 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
707 tcg_target_long offset)
708 {
709 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
710 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
711 }
712
tcg_gen_ld16s_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)713 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
714 tcg_target_long offset)
715 {
716 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
717 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
718 }
719
tcg_gen_ld32u_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)720 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
721 tcg_target_long offset)
722 {
723 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
724 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
725 }
726
tcg_gen_ld32s_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)727 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
728 tcg_target_long offset)
729 {
730 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
731 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
732 }
733
tcg_gen_ld_i64(TCGv_i64 ret,TCGv_ptr arg2,tcg_target_long offset)734 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
735 tcg_target_long offset)
736 {
737 /* since arg2 and ret have different types, they cannot be the
738 same temporary */
739 #ifdef TCG_TARGET_WORDS_BIGENDIAN
740 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
741 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
742 #else
743 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
744 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
745 #endif
746 }
747
tcg_gen_st8_i64(TCGv_i64 arg1,TCGv_ptr arg2,tcg_target_long offset)748 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
749 tcg_target_long offset)
750 {
751 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
752 }
753
tcg_gen_st16_i64(TCGv_i64 arg1,TCGv_ptr arg2,tcg_target_long offset)754 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
755 tcg_target_long offset)
756 {
757 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
758 }
759
tcg_gen_st32_i64(TCGv_i64 arg1,TCGv_ptr arg2,tcg_target_long offset)760 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
761 tcg_target_long offset)
762 {
763 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
764 }
765
tcg_gen_st_i64(TCGv_i64 arg1,TCGv_ptr arg2,tcg_target_long offset)766 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
767 tcg_target_long offset)
768 {
769 #ifdef TCG_TARGET_WORDS_BIGENDIAN
770 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
771 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
772 #else
773 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
774 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
775 #endif
776 }
777
tcg_gen_add_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)778 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
779 {
780 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
781 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
782 TCGV_HIGH(arg2));
783 }
784
tcg_gen_sub_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)785 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
786 {
787 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
788 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
789 TCGV_HIGH(arg2));
790 }
791
tcg_gen_and_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)792 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
793 {
794 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
795 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
796 }
797
tcg_gen_andi_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)798 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
799 {
800 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
801 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
802 }
803
tcg_gen_or_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)804 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
805 {
806 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
807 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
808 }
809
tcg_gen_ori_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)810 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
811 {
812 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
813 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
814 }
815
tcg_gen_xor_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)816 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
817 {
818 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
819 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
820 }
821
tcg_gen_xori_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)822 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
823 {
824 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
825 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
826 }
827
828 /* XXX: use generic code when basic block handling is OK or CPU
829 specific code (x86) */
tcg_gen_shl_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)830 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
831 {
832 tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
833 }
834
tcg_gen_shli_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)835 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
836 {
837 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
838 }
839
tcg_gen_shr_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)840 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
841 {
842 tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
843 }
844
tcg_gen_shri_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)845 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
846 {
847 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
848 }
849
tcg_gen_sar_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)850 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
851 {
852 tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
853 }
854
tcg_gen_sari_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)855 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
856 {
857 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
858 }
859
tcg_gen_brcond_i64(int cond,TCGv_i64 arg1,TCGv_i64 arg2,int label_index)860 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
861 int label_index)
862 {
863 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
864 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
865 TCGV_HIGH(arg2), cond, label_index);
866 }
867
tcg_gen_setcond_i64(int cond,TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)868 static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
869 TCGv_i64 arg1, TCGv_i64 arg2)
870 {
871 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
872 TCGV_LOW(arg1), TCGV_HIGH(arg1),
873 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
874 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
875 }
876
tcg_gen_mul_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)877 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
878 {
879 TCGv_i64 t0;
880 TCGv_i32 t1;
881
882 t0 = tcg_temp_new_i64();
883 t1 = tcg_temp_new_i32();
884
885 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
886 TCGV_LOW(arg1), TCGV_LOW(arg2));
887
888 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
889 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
890 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
891 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
892
893 tcg_gen_mov_i64(ret, t0);
894 tcg_temp_free_i64(t0);
895 tcg_temp_free_i32(t1);
896 }
897
tcg_gen_div_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)898 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
899 {
900 tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
901 }
902
tcg_gen_rem_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)903 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
904 {
905 tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
906 }
907
tcg_gen_divu_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)908 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
909 {
910 tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
911 }
912
tcg_gen_remu_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)913 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
914 {
915 tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
916 }
917
918 #else
919
tcg_gen_mov_i64(TCGv_i64 ret,TCGv_i64 arg)920 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
921 {
922 if (!TCGV_EQUAL_I64(ret, arg))
923 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
924 }
925
tcg_gen_movi_i64(TCGv_i64 ret,int64_t arg)926 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
927 {
928 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
929 }
930
tcg_gen_ld8u_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)931 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
932 tcg_target_long offset)
933 {
934 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
935 }
936
tcg_gen_ld8s_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)937 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
938 tcg_target_long offset)
939 {
940 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
941 }
942
tcg_gen_ld16u_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)943 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
944 tcg_target_long offset)
945 {
946 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
947 }
948
tcg_gen_ld16s_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)949 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
950 tcg_target_long offset)
951 {
952 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
953 }
954
tcg_gen_ld32u_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)955 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
956 tcg_target_long offset)
957 {
958 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
959 }
960
tcg_gen_ld32s_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)961 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
962 tcg_target_long offset)
963 {
964 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
965 }
966
tcg_gen_ld_i64(TCGv_i64 ret,TCGv_i64 arg2,tcg_target_long offset)967 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
968 {
969 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
970 }
971
tcg_gen_st8_i64(TCGv_i64 arg1,TCGv_i64 arg2,tcg_target_long offset)972 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
973 tcg_target_long offset)
974 {
975 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
976 }
977
tcg_gen_st16_i64(TCGv_i64 arg1,TCGv_i64 arg2,tcg_target_long offset)978 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
979 tcg_target_long offset)
980 {
981 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
982 }
983
tcg_gen_st32_i64(TCGv_i64 arg1,TCGv_i64 arg2,tcg_target_long offset)984 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
985 tcg_target_long offset)
986 {
987 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
988 }
989
tcg_gen_st_i64(TCGv_i64 arg1,TCGv_i64 arg2,tcg_target_long offset)990 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
991 {
992 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
993 }
994
tcg_gen_add_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)995 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
996 {
997 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
998 }
999
tcg_gen_sub_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1000 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1001 {
1002 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1003 }
1004
tcg_gen_and_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1005 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1006 {
1007 if (TCGV_EQUAL_I64(arg1, arg2)) {
1008 tcg_gen_mov_i64(ret, arg1);
1009 } else {
1010 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1011 }
1012 }
1013
tcg_gen_andi_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1014 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1015 {
1016 TCGv_i64 t0 = tcg_const_i64(arg2);
1017 tcg_gen_and_i64(ret, arg1, t0);
1018 tcg_temp_free_i64(t0);
1019 }
1020
tcg_gen_or_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1021 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1022 {
1023 if (TCGV_EQUAL_I64(arg1, arg2)) {
1024 tcg_gen_mov_i64(ret, arg1);
1025 } else {
1026 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1027 }
1028 }
1029
tcg_gen_ori_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1030 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1031 {
1032 TCGv_i64 t0 = tcg_const_i64(arg2);
1033 tcg_gen_or_i64(ret, arg1, t0);
1034 tcg_temp_free_i64(t0);
1035 }
1036
tcg_gen_xor_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1037 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1038 {
1039 if (TCGV_EQUAL_I64(arg1, arg2)) {
1040 tcg_gen_movi_i64(ret, 0);
1041 } else {
1042 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1043 }
1044 }
1045
tcg_gen_xori_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1046 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1047 {
1048 TCGv_i64 t0 = tcg_const_i64(arg2);
1049 tcg_gen_xor_i64(ret, arg1, t0);
1050 tcg_temp_free_i64(t0);
1051 }
1052
tcg_gen_shl_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1053 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1054 {
1055 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1056 }
1057
tcg_gen_shli_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1058 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1059 {
1060 if (arg2 == 0) {
1061 tcg_gen_mov_i64(ret, arg1);
1062 } else {
1063 TCGv_i64 t0 = tcg_const_i64(arg2);
1064 tcg_gen_shl_i64(ret, arg1, t0);
1065 tcg_temp_free_i64(t0);
1066 }
1067 }
1068
tcg_gen_shr_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1069 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1070 {
1071 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1072 }
1073
tcg_gen_shri_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1074 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1075 {
1076 if (arg2 == 0) {
1077 tcg_gen_mov_i64(ret, arg1);
1078 } else {
1079 TCGv_i64 t0 = tcg_const_i64(arg2);
1080 tcg_gen_shr_i64(ret, arg1, t0);
1081 tcg_temp_free_i64(t0);
1082 }
1083 }
1084
tcg_gen_sar_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1085 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1086 {
1087 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1088 }
1089
tcg_gen_sari_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1090 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1091 {
1092 if (arg2 == 0) {
1093 tcg_gen_mov_i64(ret, arg1);
1094 } else {
1095 TCGv_i64 t0 = tcg_const_i64(arg2);
1096 tcg_gen_sar_i64(ret, arg1, t0);
1097 tcg_temp_free_i64(t0);
1098 }
1099 }
1100
tcg_gen_brcond_i64(int cond,TCGv_i64 arg1,TCGv_i64 arg2,int label_index)1101 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1102 int label_index)
1103 {
1104 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1105 }
1106
tcg_gen_setcond_i64(int cond,TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1107 static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
1108 TCGv_i64 arg1, TCGv_i64 arg2)
1109 {
1110 tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1111 }
1112
tcg_gen_mul_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1113 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1114 {
1115 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1116 }
1117
1118 #ifdef TCG_TARGET_HAS_div_i64
tcg_gen_div_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1119 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1120 {
1121 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1122 }
1123
tcg_gen_rem_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1124 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1125 {
1126 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1127 }
1128
tcg_gen_divu_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1129 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1130 {
1131 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1132 }
1133
tcg_gen_remu_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1134 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1135 {
1136 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1137 }
1138 #else
tcg_gen_div_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1139 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1140 {
1141 TCGv_i64 t0;
1142 t0 = tcg_temp_new_i64();
1143 tcg_gen_sari_i64(t0, arg1, 63);
1144 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1145 tcg_temp_free_i64(t0);
1146 }
1147
tcg_gen_rem_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1148 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1149 {
1150 TCGv_i64 t0;
1151 t0 = tcg_temp_new_i64();
1152 tcg_gen_sari_i64(t0, arg1, 63);
1153 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1154 tcg_temp_free_i64(t0);
1155 }
1156
tcg_gen_divu_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1157 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1158 {
1159 TCGv_i64 t0;
1160 t0 = tcg_temp_new_i64();
1161 tcg_gen_movi_i64(t0, 0);
1162 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1163 tcg_temp_free_i64(t0);
1164 }
1165
tcg_gen_remu_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1166 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1167 {
1168 TCGv_i64 t0;
1169 t0 = tcg_temp_new_i64();
1170 tcg_gen_movi_i64(t0, 0);
1171 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1172 tcg_temp_free_i64(t0);
1173 }
1174 #endif
1175
1176 #endif
1177
tcg_gen_addi_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1178 static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1179 {
1180 /* some cases can be optimized here */
1181 if (arg2 == 0) {
1182 tcg_gen_mov_i64(ret, arg1);
1183 } else {
1184 TCGv_i64 t0 = tcg_const_i64(arg2);
1185 tcg_gen_add_i64(ret, arg1, t0);
1186 tcg_temp_free_i64(t0);
1187 }
1188 }
1189
tcg_gen_subfi_i64(TCGv_i64 ret,int64_t arg1,TCGv_i64 arg2)1190 static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1191 {
1192 TCGv_i64 t0 = tcg_const_i64(arg1);
1193 tcg_gen_sub_i64(ret, t0, arg2);
1194 tcg_temp_free_i64(t0);
1195 }
1196
tcg_gen_subi_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1197 static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1198 {
1199 /* some cases can be optimized here */
1200 if (arg2 == 0) {
1201 tcg_gen_mov_i64(ret, arg1);
1202 } else {
1203 TCGv_i64 t0 = tcg_const_i64(arg2);
1204 tcg_gen_sub_i64(ret, arg1, t0);
1205 tcg_temp_free_i64(t0);
1206 }
1207 }
tcg_gen_brcondi_i64(int cond,TCGv_i64 arg1,int64_t arg2,int label_index)1208 static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1209 int label_index)
1210 {
1211 TCGv_i64 t0 = tcg_const_i64(arg2);
1212 tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1213 tcg_temp_free_i64(t0);
1214 }
1215
tcg_gen_setcondi_i64(int cond,TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1216 static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1,
1217 int64_t arg2)
1218 {
1219 TCGv_i64 t0 = tcg_const_i64(arg2);
1220 tcg_gen_setcond_i64(cond, ret, arg1, t0);
1221 tcg_temp_free_i64(t0);
1222 }
1223
tcg_gen_muli_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1224 static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1225 {
1226 TCGv_i64 t0 = tcg_const_i64(arg2);
1227 tcg_gen_mul_i64(ret, arg1, t0);
1228 tcg_temp_free_i64(t0);
1229 }
1230
1231
1232 /***************************************/
1233 /* optional operations */
1234
tcg_gen_ext8s_i32(TCGv_i32 ret,TCGv_i32 arg)1235 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1236 {
1237 #ifdef TCG_TARGET_HAS_ext8s_i32
1238 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1239 #else
1240 tcg_gen_shli_i32(ret, arg, 24);
1241 tcg_gen_sari_i32(ret, ret, 24);
1242 #endif
1243 }
1244
tcg_gen_ext16s_i32(TCGv_i32 ret,TCGv_i32 arg)1245 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1246 {
1247 #ifdef TCG_TARGET_HAS_ext16s_i32
1248 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1249 #else
1250 tcg_gen_shli_i32(ret, arg, 16);
1251 tcg_gen_sari_i32(ret, ret, 16);
1252 #endif
1253 }
1254
tcg_gen_ext8u_i32(TCGv_i32 ret,TCGv_i32 arg)1255 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1256 {
1257 #ifdef TCG_TARGET_HAS_ext8u_i32
1258 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1259 #else
1260 tcg_gen_andi_i32(ret, arg, 0xffu);
1261 #endif
1262 }
1263
tcg_gen_ext16u_i32(TCGv_i32 ret,TCGv_i32 arg)1264 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1265 {
1266 #ifdef TCG_TARGET_HAS_ext16u_i32
1267 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1268 #else
1269 tcg_gen_andi_i32(ret, arg, 0xffffu);
1270 #endif
1271 }
1272
1273 /* Note: we assume the two high bytes are set to zero */
tcg_gen_bswap16_i32(TCGv_i32 ret,TCGv_i32 arg)1274 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1275 {
1276 #ifdef TCG_TARGET_HAS_bswap16_i32
1277 tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1278 #else
1279 TCGv_i32 t0 = tcg_temp_new_i32();
1280
1281 tcg_gen_ext8u_i32(t0, arg);
1282 tcg_gen_shli_i32(t0, t0, 8);
1283 tcg_gen_shri_i32(ret, arg, 8);
1284 tcg_gen_or_i32(ret, ret, t0);
1285 tcg_temp_free_i32(t0);
1286 #endif
1287 }
1288
tcg_gen_bswap32_i32(TCGv_i32 ret,TCGv_i32 arg)1289 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1290 {
1291 #ifdef TCG_TARGET_HAS_bswap32_i32
1292 tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1293 #else
1294 TCGv_i32 t0, t1;
1295 t0 = tcg_temp_new_i32();
1296 t1 = tcg_temp_new_i32();
1297
1298 tcg_gen_shli_i32(t0, arg, 24);
1299
1300 tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1301 tcg_gen_shli_i32(t1, t1, 8);
1302 tcg_gen_or_i32(t0, t0, t1);
1303
1304 tcg_gen_shri_i32(t1, arg, 8);
1305 tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1306 tcg_gen_or_i32(t0, t0, t1);
1307
1308 tcg_gen_shri_i32(t1, arg, 24);
1309 tcg_gen_or_i32(ret, t0, t1);
1310 tcg_temp_free_i32(t0);
1311 tcg_temp_free_i32(t1);
1312 #endif
1313 }
1314
1315 #if TCG_TARGET_REG_BITS == 32
tcg_gen_ext8s_i64(TCGv_i64 ret,TCGv_i64 arg)1316 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1317 {
1318 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1319 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1320 }
1321
tcg_gen_ext16s_i64(TCGv_i64 ret,TCGv_i64 arg)1322 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1323 {
1324 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1325 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1326 }
1327
tcg_gen_ext32s_i64(TCGv_i64 ret,TCGv_i64 arg)1328 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1329 {
1330 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1331 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1332 }
1333
tcg_gen_ext8u_i64(TCGv_i64 ret,TCGv_i64 arg)1334 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1335 {
1336 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1337 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1338 }
1339
tcg_gen_ext16u_i64(TCGv_i64 ret,TCGv_i64 arg)1340 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1341 {
1342 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1343 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1344 }
1345
tcg_gen_ext32u_i64(TCGv_i64 ret,TCGv_i64 arg)1346 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1347 {
1348 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1349 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1350 }
1351
tcg_gen_trunc_i64_i32(TCGv_i32 ret,TCGv_i64 arg)1352 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1353 {
1354 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1355 }
1356
tcg_gen_extu_i32_i64(TCGv_i64 ret,TCGv_i32 arg)1357 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1358 {
1359 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1360 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1361 }
1362
tcg_gen_ext_i32_i64(TCGv_i64 ret,TCGv_i32 arg)1363 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1364 {
1365 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1366 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1367 }
1368
1369 /* Note: we assume the six high bytes are set to zero */
tcg_gen_bswap16_i64(TCGv_i64 ret,TCGv_i64 arg)1370 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1371 {
1372 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1373 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1374 }
1375
1376 /* Note: we assume the four high bytes are set to zero */
tcg_gen_bswap32_i64(TCGv_i64 ret,TCGv_i64 arg)1377 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1378 {
1379 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1380 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1381 }
1382
tcg_gen_bswap64_i64(TCGv_i64 ret,TCGv_i64 arg)1383 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1384 {
1385 TCGv_i32 t0, t1;
1386 t0 = tcg_temp_new_i32();
1387 t1 = tcg_temp_new_i32();
1388
1389 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1390 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1391 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1392 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1393 tcg_temp_free_i32(t0);
1394 tcg_temp_free_i32(t1);
1395 }
1396 #else
1397
tcg_gen_ext8s_i64(TCGv_i64 ret,TCGv_i64 arg)1398 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1399 {
1400 #ifdef TCG_TARGET_HAS_ext8s_i64
1401 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1402 #else
1403 tcg_gen_shli_i64(ret, arg, 56);
1404 tcg_gen_sari_i64(ret, ret, 56);
1405 #endif
1406 }
1407
tcg_gen_ext16s_i64(TCGv_i64 ret,TCGv_i64 arg)1408 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1409 {
1410 #ifdef TCG_TARGET_HAS_ext16s_i64
1411 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1412 #else
1413 tcg_gen_shli_i64(ret, arg, 48);
1414 tcg_gen_sari_i64(ret, ret, 48);
1415 #endif
1416 }
1417
tcg_gen_ext32s_i64(TCGv_i64 ret,TCGv_i64 arg)1418 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1419 {
1420 #ifdef TCG_TARGET_HAS_ext32s_i64
1421 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1422 #else
1423 tcg_gen_shli_i64(ret, arg, 32);
1424 tcg_gen_sari_i64(ret, ret, 32);
1425 #endif
1426 }
1427
tcg_gen_ext8u_i64(TCGv_i64 ret,TCGv_i64 arg)1428 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1429 {
1430 #ifdef TCG_TARGET_HAS_ext8u_i64
1431 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1432 #else
1433 tcg_gen_andi_i64(ret, arg, 0xffu);
1434 #endif
1435 }
1436
tcg_gen_ext16u_i64(TCGv_i64 ret,TCGv_i64 arg)1437 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1438 {
1439 #ifdef TCG_TARGET_HAS_ext16u_i64
1440 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1441 #else
1442 tcg_gen_andi_i64(ret, arg, 0xffffu);
1443 #endif
1444 }
1445
tcg_gen_ext32u_i64(TCGv_i64 ret,TCGv_i64 arg)1446 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1447 {
1448 #ifdef TCG_TARGET_HAS_ext32u_i64
1449 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1450 #else
1451 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1452 #endif
1453 }
1454
1455 /* Note: we assume the target supports move between 32 and 64 bit
1456 registers. This will probably break MIPS64 targets. */
tcg_gen_trunc_i64_i32(TCGv_i32 ret,TCGv_i64 arg)1457 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1458 {
1459 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1460 }
1461
1462 /* Note: we assume the target supports move between 32 and 64 bit
1463 registers */
tcg_gen_extu_i32_i64(TCGv_i64 ret,TCGv_i32 arg)1464 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1465 {
1466 tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1467 }
1468
1469 /* Note: we assume the target supports move between 32 and 64 bit
1470 registers */
tcg_gen_ext_i32_i64(TCGv_i64 ret,TCGv_i32 arg)1471 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1472 {
1473 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1474 }
1475
1476 /* Note: we assume the six high bytes are set to zero */
tcg_gen_bswap16_i64(TCGv_i64 ret,TCGv_i64 arg)1477 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1478 {
1479 #ifdef TCG_TARGET_HAS_bswap16_i64
1480 tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1481 #else
1482 TCGv_i64 t0 = tcg_temp_new_i64();
1483
1484 tcg_gen_ext8u_i64(t0, arg);
1485 tcg_gen_shli_i64(t0, t0, 8);
1486 tcg_gen_shri_i64(ret, arg, 8);
1487 tcg_gen_or_i64(ret, ret, t0);
1488 tcg_temp_free_i64(t0);
1489 #endif
1490 }
1491
1492 /* Note: we assume the four high bytes are set to zero */
tcg_gen_bswap32_i64(TCGv_i64 ret,TCGv_i64 arg)1493 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1494 {
1495 #ifdef TCG_TARGET_HAS_bswap32_i64
1496 tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1497 #else
1498 TCGv_i64 t0, t1;
1499 t0 = tcg_temp_new_i64();
1500 t1 = tcg_temp_new_i64();
1501
1502 tcg_gen_shli_i64(t0, arg, 24);
1503 tcg_gen_ext32u_i64(t0, t0);
1504
1505 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1506 tcg_gen_shli_i64(t1, t1, 8);
1507 tcg_gen_or_i64(t0, t0, t1);
1508
1509 tcg_gen_shri_i64(t1, arg, 8);
1510 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1511 tcg_gen_or_i64(t0, t0, t1);
1512
1513 tcg_gen_shri_i64(t1, arg, 24);
1514 tcg_gen_or_i64(ret, t0, t1);
1515 tcg_temp_free_i64(t0);
1516 tcg_temp_free_i64(t1);
1517 #endif
1518 }
1519
tcg_gen_bswap64_i64(TCGv_i64 ret,TCGv_i64 arg)1520 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1521 {
1522 #ifdef TCG_TARGET_HAS_bswap64_i64
1523 tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1524 #else
1525 TCGv_i64 t0 = tcg_temp_new_i64();
1526 TCGv_i64 t1 = tcg_temp_new_i64();
1527
1528 tcg_gen_shli_i64(t0, arg, 56);
1529
1530 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1531 tcg_gen_shli_i64(t1, t1, 40);
1532 tcg_gen_or_i64(t0, t0, t1);
1533
1534 tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1535 tcg_gen_shli_i64(t1, t1, 24);
1536 tcg_gen_or_i64(t0, t0, t1);
1537
1538 tcg_gen_andi_i64(t1, arg, 0xff000000);
1539 tcg_gen_shli_i64(t1, t1, 8);
1540 tcg_gen_or_i64(t0, t0, t1);
1541
1542 tcg_gen_shri_i64(t1, arg, 8);
1543 tcg_gen_andi_i64(t1, t1, 0xff000000);
1544 tcg_gen_or_i64(t0, t0, t1);
1545
1546 tcg_gen_shri_i64(t1, arg, 24);
1547 tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1548 tcg_gen_or_i64(t0, t0, t1);
1549
1550 tcg_gen_shri_i64(t1, arg, 40);
1551 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1552 tcg_gen_or_i64(t0, t0, t1);
1553
1554 tcg_gen_shri_i64(t1, arg, 56);
1555 tcg_gen_or_i64(ret, t0, t1);
1556 tcg_temp_free_i64(t0);
1557 tcg_temp_free_i64(t1);
1558 #endif
1559 }
1560
1561 #endif
1562
tcg_gen_neg_i32(TCGv_i32 ret,TCGv_i32 arg)1563 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1564 {
1565 #ifdef TCG_TARGET_HAS_neg_i32
1566 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1567 #else
1568 TCGv_i32 t0 = tcg_const_i32(0);
1569 tcg_gen_sub_i32(ret, t0, arg);
1570 tcg_temp_free_i32(t0);
1571 #endif
1572 }
1573
tcg_gen_neg_i64(TCGv_i64 ret,TCGv_i64 arg)1574 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1575 {
1576 #ifdef TCG_TARGET_HAS_neg_i64
1577 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1578 #else
1579 TCGv_i64 t0 = tcg_const_i64(0);
1580 tcg_gen_sub_i64(ret, t0, arg);
1581 tcg_temp_free_i64(t0);
1582 #endif
1583 }
1584
tcg_gen_not_i32(TCGv_i32 ret,TCGv_i32 arg)1585 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1586 {
1587 #ifdef TCG_TARGET_HAS_not_i32
1588 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1589 #else
1590 tcg_gen_xori_i32(ret, arg, -1);
1591 #endif
1592 }
1593
tcg_gen_not_i64(TCGv_i64 ret,TCGv_i64 arg)1594 static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1595 {
1596 #ifdef TCG_TARGET_HAS_not_i64
1597 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1598 #else
1599 tcg_gen_xori_i64(ret, arg, -1);
1600 #endif
1601 }
1602
tcg_gen_discard_i32(TCGv_i32 arg)1603 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1604 {
1605 tcg_gen_op1_i32(INDEX_op_discard, arg);
1606 }
1607
1608 #if TCG_TARGET_REG_BITS == 32
tcg_gen_discard_i64(TCGv_i64 arg)1609 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1610 {
1611 tcg_gen_discard_i32(TCGV_LOW(arg));
1612 tcg_gen_discard_i32(TCGV_HIGH(arg));
1613 }
1614 #else
tcg_gen_discard_i64(TCGv_i64 arg)1615 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1616 {
1617 tcg_gen_op1_i64(INDEX_op_discard, arg);
1618 }
1619 #endif
1620
tcg_gen_concat_i32_i64(TCGv_i64 dest,TCGv_i32 low,TCGv_i32 high)1621 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1622 {
1623 #if TCG_TARGET_REG_BITS == 32
1624 tcg_gen_mov_i32(TCGV_LOW(dest), low);
1625 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1626 #else
1627 TCGv_i64 tmp = tcg_temp_new_i64();
1628 /* This extension is only needed for type correctness.
1629 We may be able to do better given target specific information. */
1630 tcg_gen_extu_i32_i64(tmp, high);
1631 tcg_gen_shli_i64(tmp, tmp, 32);
1632 tcg_gen_extu_i32_i64(dest, low);
1633 tcg_gen_or_i64(dest, dest, tmp);
1634 tcg_temp_free_i64(tmp);
1635 #endif
1636 }
1637
tcg_gen_concat32_i64(TCGv_i64 dest,TCGv_i64 low,TCGv_i64 high)1638 static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1639 {
1640 #if TCG_TARGET_REG_BITS == 32
1641 tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1642 #else
1643 TCGv_i64 tmp = tcg_temp_new_i64();
1644 tcg_gen_ext32u_i64(dest, low);
1645 tcg_gen_shli_i64(tmp, high, 32);
1646 tcg_gen_or_i64(dest, dest, tmp);
1647 tcg_temp_free_i64(tmp);
1648 #endif
1649 }
1650
tcg_gen_andc_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1651 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1652 {
1653 #ifdef TCG_TARGET_HAS_andc_i32
1654 tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1655 #else
1656 TCGv_i32 t0;
1657 t0 = tcg_temp_new_i32();
1658 tcg_gen_not_i32(t0, arg2);
1659 tcg_gen_and_i32(ret, arg1, t0);
1660 tcg_temp_free_i32(t0);
1661 #endif
1662 }
1663
tcg_gen_andc_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1664 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1665 {
1666 #ifdef TCG_TARGET_HAS_andc_i64
1667 tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1668 #elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
1669 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1670 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1671 #else
1672 TCGv_i64 t0;
1673 t0 = tcg_temp_new_i64();
1674 tcg_gen_not_i64(t0, arg2);
1675 tcg_gen_and_i64(ret, arg1, t0);
1676 tcg_temp_free_i64(t0);
1677 #endif
1678 }
1679
tcg_gen_eqv_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1680 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1681 {
1682 tcg_gen_xor_i32(ret, arg1, arg2);
1683 tcg_gen_not_i32(ret, ret);
1684 }
1685
tcg_gen_eqv_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1686 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1687 {
1688 tcg_gen_xor_i64(ret, arg1, arg2);
1689 tcg_gen_not_i64(ret, ret);
1690 }
1691
tcg_gen_nand_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1692 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1693 {
1694 tcg_gen_and_i32(ret, arg1, arg2);
1695 tcg_gen_not_i32(ret, ret);
1696 }
1697
tcg_gen_nand_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1698 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1699 {
1700 tcg_gen_and_i64(ret, arg1, arg2);
1701 tcg_gen_not_i64(ret, ret);
1702 }
1703
tcg_gen_nor_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1704 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1705 {
1706 tcg_gen_or_i32(ret, arg1, arg2);
1707 tcg_gen_not_i32(ret, ret);
1708 }
1709
tcg_gen_nor_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1710 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1711 {
1712 tcg_gen_or_i64(ret, arg1, arg2);
1713 tcg_gen_not_i64(ret, ret);
1714 }
1715
tcg_gen_orc_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1716 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1717 {
1718 #ifdef TCG_TARGET_HAS_orc_i32
1719 tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1720 #else
1721 TCGv_i32 t0;
1722 t0 = tcg_temp_new_i32();
1723 tcg_gen_not_i32(t0, arg2);
1724 tcg_gen_or_i32(ret, arg1, t0);
1725 tcg_temp_free_i32(t0);
1726 #endif
1727 }
1728
tcg_gen_orc_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1729 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1730 {
1731 #ifdef TCG_TARGET_HAS_orc_i64
1732 tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1733 #elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
1734 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1735 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1736 #else
1737 TCGv_i64 t0;
1738 t0 = tcg_temp_new_i64();
1739 tcg_gen_not_i64(t0, arg2);
1740 tcg_gen_or_i64(ret, arg1, t0);
1741 tcg_temp_free_i64(t0);
1742 #endif
1743 }
1744
tcg_gen_rotl_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1745 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1746 {
1747 #ifdef TCG_TARGET_HAS_rot_i32
1748 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1749 #else
1750 TCGv_i32 t0, t1;
1751
1752 t0 = tcg_temp_new_i32();
1753 t1 = tcg_temp_new_i32();
1754 tcg_gen_shl_i32(t0, arg1, arg2);
1755 tcg_gen_subfi_i32(t1, 32, arg2);
1756 tcg_gen_shr_i32(t1, arg1, t1);
1757 tcg_gen_or_i32(ret, t0, t1);
1758 tcg_temp_free_i32(t0);
1759 tcg_temp_free_i32(t1);
1760 #endif
1761 }
1762
tcg_gen_rotl_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1763 static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1764 {
1765 #ifdef TCG_TARGET_HAS_rot_i64
1766 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1767 #else
1768 TCGv_i64 t0, t1;
1769
1770 t0 = tcg_temp_new_i64();
1771 t1 = tcg_temp_new_i64();
1772 tcg_gen_shl_i64(t0, arg1, arg2);
1773 tcg_gen_subfi_i64(t1, 64, arg2);
1774 tcg_gen_shr_i64(t1, arg1, t1);
1775 tcg_gen_or_i64(ret, t0, t1);
1776 tcg_temp_free_i64(t0);
1777 tcg_temp_free_i64(t1);
1778 #endif
1779 }
1780
tcg_gen_rotli_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)1781 static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1782 {
1783 /* some cases can be optimized here */
1784 if (arg2 == 0) {
1785 tcg_gen_mov_i32(ret, arg1);
1786 } else {
1787 #ifdef TCG_TARGET_HAS_rot_i32
1788 TCGv_i32 t0 = tcg_const_i32(arg2);
1789 tcg_gen_rotl_i32(ret, arg1, t0);
1790 tcg_temp_free_i32(t0);
1791 #else
1792 TCGv_i32 t0, t1;
1793 t0 = tcg_temp_new_i32();
1794 t1 = tcg_temp_new_i32();
1795 tcg_gen_shli_i32(t0, arg1, arg2);
1796 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1797 tcg_gen_or_i32(ret, t0, t1);
1798 tcg_temp_free_i32(t0);
1799 tcg_temp_free_i32(t1);
1800 #endif
1801 }
1802 }
1803
tcg_gen_rotli_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1804 static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1805 {
1806 /* some cases can be optimized here */
1807 if (arg2 == 0) {
1808 tcg_gen_mov_i64(ret, arg1);
1809 } else {
1810 #ifdef TCG_TARGET_HAS_rot_i64
1811 TCGv_i64 t0 = tcg_const_i64(arg2);
1812 tcg_gen_rotl_i64(ret, arg1, t0);
1813 tcg_temp_free_i64(t0);
1814 #else
1815 TCGv_i64 t0, t1;
1816 t0 = tcg_temp_new_i64();
1817 t1 = tcg_temp_new_i64();
1818 tcg_gen_shli_i64(t0, arg1, arg2);
1819 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1820 tcg_gen_or_i64(ret, t0, t1);
1821 tcg_temp_free_i64(t0);
1822 tcg_temp_free_i64(t1);
1823 #endif
1824 }
1825 }
1826
tcg_gen_rotr_i32(TCGv_i32 ret,TCGv_i32 arg1,TCGv_i32 arg2)1827 static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1828 {
1829 #ifdef TCG_TARGET_HAS_rot_i32
1830 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1831 #else
1832 TCGv_i32 t0, t1;
1833
1834 t0 = tcg_temp_new_i32();
1835 t1 = tcg_temp_new_i32();
1836 tcg_gen_shr_i32(t0, arg1, arg2);
1837 tcg_gen_subfi_i32(t1, 32, arg2);
1838 tcg_gen_shl_i32(t1, arg1, t1);
1839 tcg_gen_or_i32(ret, t0, t1);
1840 tcg_temp_free_i32(t0);
1841 tcg_temp_free_i32(t1);
1842 #endif
1843 }
1844
tcg_gen_rotr_i64(TCGv_i64 ret,TCGv_i64 arg1,TCGv_i64 arg2)1845 static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1846 {
1847 #ifdef TCG_TARGET_HAS_rot_i64
1848 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
1849 #else
1850 TCGv_i64 t0, t1;
1851
1852 t0 = tcg_temp_new_i64();
1853 t1 = tcg_temp_new_i64();
1854 tcg_gen_shr_i64(t0, arg1, arg2);
1855 tcg_gen_subfi_i64(t1, 64, arg2);
1856 tcg_gen_shl_i64(t1, arg1, t1);
1857 tcg_gen_or_i64(ret, t0, t1);
1858 tcg_temp_free_i64(t0);
1859 tcg_temp_free_i64(t1);
1860 #endif
1861 }
1862
tcg_gen_rotri_i32(TCGv_i32 ret,TCGv_i32 arg1,int32_t arg2)1863 static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1864 {
1865 /* some cases can be optimized here */
1866 if (arg2 == 0) {
1867 tcg_gen_mov_i32(ret, arg1);
1868 } else {
1869 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1870 }
1871 }
1872
tcg_gen_rotri_i64(TCGv_i64 ret,TCGv_i64 arg1,int64_t arg2)1873 static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1874 {
1875 /* some cases can be optimized here */
1876 if (arg2 == 0) {
1877 tcg_gen_mov_i64(ret, arg1);
1878 } else {
1879 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1880 }
1881 }
1882
1883 /***************************************/
1884 /* QEMU specific operations. Their type depend on the QEMU CPU
1885 type. */
1886 #ifndef TARGET_LONG_BITS
1887 #error must include QEMU headers
1888 #endif
1889
1890 #if TARGET_LONG_BITS == 32
1891 #define TCGv TCGv_i32
1892 #define tcg_temp_new() tcg_temp_new_i32()
1893 #define tcg_global_reg_new tcg_global_reg_new_i32
1894 #define tcg_global_mem_new tcg_global_mem_new_i32
1895 #define tcg_temp_local_new() tcg_temp_local_new_i32()
1896 #define tcg_temp_free tcg_temp_free_i32
1897 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1898 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1899 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1900 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1901 #else
1902 #define TCGv TCGv_i64
1903 #define tcg_temp_new() tcg_temp_new_i64()
1904 #define tcg_global_reg_new tcg_global_reg_new_i64
1905 #define tcg_global_mem_new tcg_global_mem_new_i64
1906 #define tcg_temp_local_new() tcg_temp_local_new_i64()
1907 #define tcg_temp_free tcg_temp_free_i64
1908 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1909 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1910 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1911 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1912 #endif
1913
1914 /* debug info: write the PC of the corresponding QEMU CPU instruction */
tcg_gen_debug_insn_start(uint64_t pc)1915 static inline void tcg_gen_debug_insn_start(uint64_t pc)
1916 {
1917 /* XXX: must really use a 32 bit size for TCGArg in all cases */
1918 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1919 tcg_gen_op2ii(INDEX_op_debug_insn_start,
1920 (uint32_t)(pc), (uint32_t)(pc >> 32));
1921 #else
1922 tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1923 #endif
1924 }
1925
tcg_gen_exit_tb(tcg_target_long val)1926 static inline void tcg_gen_exit_tb(tcg_target_long val)
1927 {
1928 tcg_gen_op1i(INDEX_op_exit_tb, val);
1929 }
1930
tcg_gen_goto_tb(int idx)1931 static inline void tcg_gen_goto_tb(int idx)
1932 {
1933 tcg_gen_op1i(INDEX_op_goto_tb, idx);
1934 }
1935
1936 #if TCG_TARGET_REG_BITS == 32
tcg_gen_qemu_ld8u(TCGv ret,TCGv addr,int mem_index)1937 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1938 {
1939 #if TARGET_LONG_BITS == 32
1940 tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1941 #else
1942 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1943 TCGV_HIGH(addr), mem_index);
1944 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1945 #endif
1946 }
1947
tcg_gen_qemu_ld8s(TCGv ret,TCGv addr,int mem_index)1948 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1949 {
1950 #if TARGET_LONG_BITS == 32
1951 tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1952 #else
1953 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1954 TCGV_HIGH(addr), mem_index);
1955 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1956 #endif
1957 }
1958
tcg_gen_qemu_ld16u(TCGv ret,TCGv addr,int mem_index)1959 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1960 {
1961 #if TARGET_LONG_BITS == 32
1962 tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1963 #else
1964 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1965 TCGV_HIGH(addr), mem_index);
1966 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1967 #endif
1968 }
1969
tcg_gen_qemu_ld16s(TCGv ret,TCGv addr,int mem_index)1970 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1971 {
1972 #if TARGET_LONG_BITS == 32
1973 tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1974 #else
1975 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1976 TCGV_HIGH(addr), mem_index);
1977 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1978 #endif
1979 }
1980
tcg_gen_qemu_ld32u(TCGv ret,TCGv addr,int mem_index)1981 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1982 {
1983 #if TARGET_LONG_BITS == 32
1984 tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1985 #else
1986 tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1987 TCGV_HIGH(addr), mem_index);
1988 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1989 #endif
1990 }
1991
tcg_gen_qemu_ld32s(TCGv ret,TCGv addr,int mem_index)1992 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1993 {
1994 #if TARGET_LONG_BITS == 32
1995 tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1996 #else
1997 tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1998 TCGV_HIGH(addr), mem_index);
1999 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2000 #endif
2001 }
2002
tcg_gen_qemu_ld64(TCGv_i64 ret,TCGv addr,int mem_index)2003 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2004 {
2005 #if TARGET_LONG_BITS == 32
2006 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2007 #else
2008 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2009 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2010 #endif
2011 }
2012
tcg_gen_qemu_st8(TCGv arg,TCGv addr,int mem_index)2013 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2014 {
2015 #if TARGET_LONG_BITS == 32
2016 tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2017 #else
2018 tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2019 TCGV_HIGH(addr), mem_index);
2020 #endif
2021 }
2022
tcg_gen_qemu_st16(TCGv arg,TCGv addr,int mem_index)2023 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2024 {
2025 #if TARGET_LONG_BITS == 32
2026 tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2027 #else
2028 tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2029 TCGV_HIGH(addr), mem_index);
2030 #endif
2031 }
2032
tcg_gen_qemu_st32(TCGv arg,TCGv addr,int mem_index)2033 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2034 {
2035 #if TARGET_LONG_BITS == 32
2036 tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2037 #else
2038 tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2039 TCGV_HIGH(addr), mem_index);
2040 #endif
2041 }
2042
tcg_gen_qemu_st64(TCGv_i64 arg,TCGv addr,int mem_index)2043 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2044 {
2045 #if TARGET_LONG_BITS == 32
2046 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2047 mem_index);
2048 #else
2049 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2050 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2051 #endif
2052 }
2053
2054 #define tcg_gen_ld_ptr tcg_gen_ld_i32
2055 #define tcg_gen_discard_ptr tcg_gen_discard_i32
2056
2057 #else /* TCG_TARGET_REG_BITS == 32 */
2058
tcg_gen_qemu_ld8u(TCGv ret,TCGv addr,int mem_index)2059 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2060 {
2061 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2062 }
2063
tcg_gen_qemu_ld8s(TCGv ret,TCGv addr,int mem_index)2064 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2065 {
2066 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2067 }
2068
tcg_gen_qemu_ld16u(TCGv ret,TCGv addr,int mem_index)2069 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2070 {
2071 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2072 }
2073
tcg_gen_qemu_ld16s(TCGv ret,TCGv addr,int mem_index)2074 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2075 {
2076 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2077 }
2078
tcg_gen_qemu_ld32u(TCGv ret,TCGv addr,int mem_index)2079 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2080 {
2081 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2082 }
2083
tcg_gen_qemu_ld32s(TCGv ret,TCGv addr,int mem_index)2084 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2085 {
2086 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2087 }
2088
tcg_gen_qemu_ld64(TCGv_i64 ret,TCGv addr,int mem_index)2089 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2090 {
2091 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2092 }
2093
tcg_gen_qemu_st8(TCGv arg,TCGv addr,int mem_index)2094 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2095 {
2096 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2097 }
2098
tcg_gen_qemu_st16(TCGv arg,TCGv addr,int mem_index)2099 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2100 {
2101 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2102 }
2103
tcg_gen_qemu_st32(TCGv arg,TCGv addr,int mem_index)2104 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2105 {
2106 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2107 }
2108
tcg_gen_qemu_st64(TCGv_i64 arg,TCGv addr,int mem_index)2109 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2110 {
2111 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2112 }
2113
2114 #define tcg_gen_ld_ptr tcg_gen_ld_i64
2115 #define tcg_gen_discard_ptr tcg_gen_discard_i64
2116
2117 #endif /* TCG_TARGET_REG_BITS != 32 */
2118
2119 #if TARGET_LONG_BITS == 64
2120 #define TCG_TYPE_TL TCG_TYPE_I64
2121 #define tcg_gen_movi_tl tcg_gen_movi_i64
2122 #define tcg_gen_mov_tl tcg_gen_mov_i64
2123 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2124 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2125 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2126 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2127 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2128 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2129 #define tcg_gen_ld_tl tcg_gen_ld_i64
2130 #define tcg_gen_st8_tl tcg_gen_st8_i64
2131 #define tcg_gen_st16_tl tcg_gen_st16_i64
2132 #define tcg_gen_st32_tl tcg_gen_st32_i64
2133 #define tcg_gen_st_tl tcg_gen_st_i64
2134 #define tcg_gen_add_tl tcg_gen_add_i64
2135 #define tcg_gen_addi_tl tcg_gen_addi_i64
2136 #define tcg_gen_sub_tl tcg_gen_sub_i64
2137 #define tcg_gen_neg_tl tcg_gen_neg_i64
2138 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2139 #define tcg_gen_subi_tl tcg_gen_subi_i64
2140 #define tcg_gen_and_tl tcg_gen_and_i64
2141 #define tcg_gen_andi_tl tcg_gen_andi_i64
2142 #define tcg_gen_or_tl tcg_gen_or_i64
2143 #define tcg_gen_ori_tl tcg_gen_ori_i64
2144 #define tcg_gen_xor_tl tcg_gen_xor_i64
2145 #define tcg_gen_xori_tl tcg_gen_xori_i64
2146 #define tcg_gen_not_tl tcg_gen_not_i64
2147 #define tcg_gen_shl_tl tcg_gen_shl_i64
2148 #define tcg_gen_shli_tl tcg_gen_shli_i64
2149 #define tcg_gen_shr_tl tcg_gen_shr_i64
2150 #define tcg_gen_shri_tl tcg_gen_shri_i64
2151 #define tcg_gen_sar_tl tcg_gen_sar_i64
2152 #define tcg_gen_sari_tl tcg_gen_sari_i64
2153 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2154 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2155 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
2156 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2157 #define tcg_gen_mul_tl tcg_gen_mul_i64
2158 #define tcg_gen_muli_tl tcg_gen_muli_i64
2159 #define tcg_gen_div_tl tcg_gen_div_i64
2160 #define tcg_gen_rem_tl tcg_gen_rem_i64
2161 #define tcg_gen_divu_tl tcg_gen_divu_i64
2162 #define tcg_gen_remu_tl tcg_gen_remu_i64
2163 #define tcg_gen_discard_tl tcg_gen_discard_i64
2164 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2165 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2166 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2167 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2168 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2169 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2170 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2171 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2172 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2173 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2174 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2175 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2176 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2177 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2178 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2179 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2180 #define tcg_gen_andc_tl tcg_gen_andc_i64
2181 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2182 #define tcg_gen_nand_tl tcg_gen_nand_i64
2183 #define tcg_gen_nor_tl tcg_gen_nor_i64
2184 #define tcg_gen_orc_tl tcg_gen_orc_i64
2185 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2186 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2187 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2188 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2189 #define tcg_const_tl tcg_const_i64
2190 #define tcg_const_local_tl tcg_const_local_i64
2191 #else
2192 #define TCG_TYPE_TL TCG_TYPE_I32
2193 #define tcg_gen_movi_tl tcg_gen_movi_i32
2194 #define tcg_gen_mov_tl tcg_gen_mov_i32
2195 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2196 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2197 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2198 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2199 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2200 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2201 #define tcg_gen_ld_tl tcg_gen_ld_i32
2202 #define tcg_gen_st8_tl tcg_gen_st8_i32
2203 #define tcg_gen_st16_tl tcg_gen_st16_i32
2204 #define tcg_gen_st32_tl tcg_gen_st_i32
2205 #define tcg_gen_st_tl tcg_gen_st_i32
2206 #define tcg_gen_add_tl tcg_gen_add_i32
2207 #define tcg_gen_addi_tl tcg_gen_addi_i32
2208 #define tcg_gen_sub_tl tcg_gen_sub_i32
2209 #define tcg_gen_neg_tl tcg_gen_neg_i32
2210 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2211 #define tcg_gen_subi_tl tcg_gen_subi_i32
2212 #define tcg_gen_and_tl tcg_gen_and_i32
2213 #define tcg_gen_andi_tl tcg_gen_andi_i32
2214 #define tcg_gen_or_tl tcg_gen_or_i32
2215 #define tcg_gen_ori_tl tcg_gen_ori_i32
2216 #define tcg_gen_xor_tl tcg_gen_xor_i32
2217 #define tcg_gen_xori_tl tcg_gen_xori_i32
2218 #define tcg_gen_not_tl tcg_gen_not_i32
2219 #define tcg_gen_shl_tl tcg_gen_shl_i32
2220 #define tcg_gen_shli_tl tcg_gen_shli_i32
2221 #define tcg_gen_shr_tl tcg_gen_shr_i32
2222 #define tcg_gen_shri_tl tcg_gen_shri_i32
2223 #define tcg_gen_sar_tl tcg_gen_sar_i32
2224 #define tcg_gen_sari_tl tcg_gen_sari_i32
2225 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2226 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2227 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
2228 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2229 #define tcg_gen_mul_tl tcg_gen_mul_i32
2230 #define tcg_gen_muli_tl tcg_gen_muli_i32
2231 #define tcg_gen_div_tl tcg_gen_div_i32
2232 #define tcg_gen_rem_tl tcg_gen_rem_i32
2233 #define tcg_gen_divu_tl tcg_gen_divu_i32
2234 #define tcg_gen_remu_tl tcg_gen_remu_i32
2235 #define tcg_gen_discard_tl tcg_gen_discard_i32
2236 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2237 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2238 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2239 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2240 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2241 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2242 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2243 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2244 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2245 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2246 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2247 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2248 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2249 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2250 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2251 #define tcg_gen_andc_tl tcg_gen_andc_i32
2252 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2253 #define tcg_gen_nand_tl tcg_gen_nand_i32
2254 #define tcg_gen_nor_tl tcg_gen_nor_i32
2255 #define tcg_gen_orc_tl tcg_gen_orc_i32
2256 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2257 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2258 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2259 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2260 #define tcg_const_tl tcg_const_i32
2261 #define tcg_const_local_tl tcg_const_local_i32
2262 #endif
2263
2264 #if TCG_TARGET_REG_BITS == 32
2265 #define tcg_gen_add_ptr tcg_gen_add_i32
2266 #define tcg_gen_addi_ptr tcg_gen_addi_i32
2267 #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2268 #else /* TCG_TARGET_REG_BITS == 32 */
2269 #define tcg_gen_add_ptr tcg_gen_add_i64
2270 #define tcg_gen_addi_ptr tcg_gen_addi_i64
2271 #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2272 #endif /* TCG_TARGET_REG_BITS != 32 */
2273