1 /*
2 * linux/include/linux/mtd/nand.h
3 *
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Info:
15 * Contains standard defines and IDs for NAND flash devices
16 *
17 * Changelog:
18 * See git changelog.
19 */
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
22
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
26
27 struct mtd_info;
28 /* Scan and identify a NAND device */
29 extern int nand_scan (struct mtd_info *mtd, int max_chips);
30 /* Free resources held by the NAND device */
31 extern void nand_release (struct mtd_info *mtd);
32
33 /* The maximum number of NAND chips in an array */
34 #define NAND_MAX_CHIPS 8
35
36 /* This constant declares the max. oobsize / page, which
37 * is supported now. If you add a chip with bigger oobsize/page
38 * adjust this accordingly.
39 */
40 #define NAND_MAX_OOBSIZE 64
41 #define NAND_MAX_PAGESIZE 2048
42
43 /*
44 * Constants for hardware specific CLE/ALE/NCE function
45 *
46 * These are bits which can be or'ed to set/clear multiple
47 * bits in one go.
48 */
49 /* Select the chip by setting nCE to low */
50 #define NAND_NCE 0x01
51 /* Select the command latch by setting CLE to high */
52 #define NAND_CLE 0x02
53 /* Select the address latch by setting ALE to high */
54 #define NAND_ALE 0x04
55
56 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
57 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
58 #define NAND_CTRL_CHANGE 0x80
59
60 /*
61 * Standard NAND flash commands
62 */
63 #define NAND_CMD_READ0 0
64 #define NAND_CMD_READ1 1
65 #define NAND_CMD_RNDOUT 5
66 #define NAND_CMD_PAGEPROG 0x10
67 #define NAND_CMD_READOOB 0x50
68 #define NAND_CMD_ERASE1 0x60
69 #define NAND_CMD_STATUS 0x70
70 #define NAND_CMD_STATUS_MULTI 0x71
71 #define NAND_CMD_SEQIN 0x80
72 #define NAND_CMD_RNDIN 0x85
73 #define NAND_CMD_READID 0x90
74 #define NAND_CMD_ERASE2 0xd0
75 #define NAND_CMD_RESET 0xff
76
77 /* Extended commands for large page devices */
78 #define NAND_CMD_READSTART 0x30
79 #define NAND_CMD_RNDOUTSTART 0xE0
80 #define NAND_CMD_CACHEDPROG 0x15
81
82 /* Extended commands for AG-AND device */
83 /*
84 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
85 * there is no way to distinguish that from NAND_CMD_READ0
86 * until the remaining sequence of commands has been completed
87 * so add a high order bit and mask it off in the command.
88 */
89 #define NAND_CMD_DEPLETE1 0x100
90 #define NAND_CMD_DEPLETE2 0x38
91 #define NAND_CMD_STATUS_MULTI 0x71
92 #define NAND_CMD_STATUS_ERROR 0x72
93 /* multi-bank error status (banks 0-3) */
94 #define NAND_CMD_STATUS_ERROR0 0x73
95 #define NAND_CMD_STATUS_ERROR1 0x74
96 #define NAND_CMD_STATUS_ERROR2 0x75
97 #define NAND_CMD_STATUS_ERROR3 0x76
98 #define NAND_CMD_STATUS_RESET 0x7f
99 #define NAND_CMD_STATUS_CLEAR 0xff
100
101 #define NAND_CMD_NONE -1
102
103 /* Status bits */
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
109
110 /*
111 * Constants for ECC_MODES
112 */
113 typedef enum {
114 NAND_ECC_NONE,
115 NAND_ECC_SOFT,
116 NAND_ECC_HW,
117 NAND_ECC_HW_SYNDROME,
118 } nand_ecc_modes_t;
119
120 /*
121 * Constants for Hardware ECC
122 */
123 /* Reset Hardware ECC for read */
124 #define NAND_ECC_READ 0
125 /* Reset Hardware ECC for write */
126 #define NAND_ECC_WRITE 1
127 /* Enable Hardware ECC before syndrom is read back from flash */
128 #define NAND_ECC_READSYN 2
129
130 /* Bit mask for flags passed to do_nand_read_ecc */
131 #define NAND_GET_DEVICE 0x80
132
133
134 /* Option constants for bizarre disfunctionality and real
135 * features
136 */
137 /* Chip can not auto increment pages */
138 #define NAND_NO_AUTOINCR 0x00000001
139 /* Buswitdh is 16 bit */
140 #define NAND_BUSWIDTH_16 0x00000002
141 /* Device supports partial programming without padding */
142 #define NAND_NO_PADDING 0x00000004
143 /* Chip has cache program function */
144 #define NAND_CACHEPRG 0x00000008
145 /* Chip has copy back function */
146 #define NAND_COPYBACK 0x00000010
147 /* AND Chip which has 4 banks and a confusing page / block
148 * assignment. See Renesas datasheet for further information */
149 #define NAND_IS_AND 0x00000020
150 /* Chip has a array of 4 pages which can be read without
151 * additional ready /busy waits */
152 #define NAND_4PAGE_ARRAY 0x00000040
153 /* Chip requires that BBT is periodically rewritten to prevent
154 * bits from adjacent blocks from 'leaking' in altering data.
155 * This happens with the Renesas AG-AND chips, possibly others. */
156 #define BBT_AUTO_REFRESH 0x00000080
157 /* Chip does not require ready check on read. True
158 * for all large page devices, as they do not support
159 * autoincrement.*/
160 #define NAND_NO_READRDY 0x00000100
161
162 /* Options valid for Samsung large page devices */
163 #define NAND_SAMSUNG_LP_OPTIONS \
164 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
165
166 /* Macros to identify the above */
167 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
168 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
169 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
170 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
171
172 /* Mask to zero out the chip options, which come from the id table */
173 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
174
175 /* Non chip related options */
176 /* Use a flash based bad block table. This option is passed to the
177 * default bad block table function. */
178 #define NAND_USE_FLASH_BBT 0x00010000
179 /* This option skips the bbt scan during initialization. */
180 #define NAND_SKIP_BBTSCAN 0x00020000
181
182 /* Options set by nand scan */
183 /* Nand scan has allocated controller struct */
184 #define NAND_CONTROLLER_ALLOC 0x80000000
185
186
187 /*
188 * nand_state_t - chip states
189 * Enumeration for NAND flash chip state
190 */
191 typedef enum {
192 FL_READY,
193 FL_READING,
194 FL_WRITING,
195 FL_ERASING,
196 FL_SYNCING,
197 FL_CACHEDPRG,
198 FL_PM_SUSPENDED,
199 } nand_state_t;
200
201 /* Keep gcc happy */
202 struct nand_chip;
203
204 /**
205 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
206 * @lock: protection lock
207 * @active: the mtd device which holds the controller currently
208 * @wq: wait queue to sleep on if a NAND operation is in progress
209 * used instead of the per chip wait queue when a hw controller is available
210 */
211 struct nand_hw_control {
212 spinlock_t lock;
213 struct nand_chip *active;
214 wait_queue_head_t wq;
215 };
216
217 /**
218 * struct nand_ecc_ctrl - Control structure for ecc
219 * @mode: ecc mode
220 * @steps: number of ecc steps per page
221 * @size: data bytes per ecc step
222 * @bytes: ecc bytes per step
223 * @total: total number of ecc bytes per page
224 * @prepad: padding information for syndrome based ecc generators
225 * @postpad: padding information for syndrome based ecc generators
226 * @layout: ECC layout control struct pointer
227 * @hwctl: function to control hardware ecc generator. Must only
228 * be provided if an hardware ECC is available
229 * @calculate: function for ecc calculation or readback from ecc hardware
230 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
231 * @read_page: function to read a page according to the ecc generator requirements
232 * @write_page: function to write a page according to the ecc generator requirements
233 * @read_oob: function to read chip OOB data
234 * @write_oob: function to write chip OOB data
235 */
236 struct nand_ecc_ctrl {
237 nand_ecc_modes_t mode;
238 int steps;
239 int size;
240 int bytes;
241 int total;
242 int prepad;
243 int postpad;
244 struct nand_ecclayout *layout;
245 void (*hwctl)(struct mtd_info *mtd, int mode);
246 int (*calculate)(struct mtd_info *mtd,
247 const uint8_t *dat,
248 uint8_t *ecc_code);
249 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
250 uint8_t *read_ecc,
251 uint8_t *calc_ecc);
252 int (*read_page)(struct mtd_info *mtd,
253 struct nand_chip *chip,
254 uint8_t *buf);
255 void (*write_page)(struct mtd_info *mtd,
256 struct nand_chip *chip,
257 const uint8_t *buf);
258 int (*read_oob)(struct mtd_info *mtd,
259 struct nand_chip *chip,
260 int page,
261 int sndcmd);
262 int (*write_oob)(struct mtd_info *mtd,
263 struct nand_chip *chip,
264 int page);
265 };
266
267 /**
268 * struct nand_buffers - buffer structure for read/write
269 * @ecccalc: buffer for calculated ecc
270 * @ecccode: buffer for ecc read from flash
271 * @oobwbuf: buffer for write oob data
272 * @databuf: buffer for data - dynamically sized
273 * @oobrbuf: buffer to read oob data
274 *
275 * Do not change the order of buffers. databuf and oobrbuf must be in
276 * consecutive order.
277 */
278 struct nand_buffers {
279 uint8_t ecccalc[NAND_MAX_OOBSIZE];
280 uint8_t ecccode[NAND_MAX_OOBSIZE];
281 uint8_t oobwbuf[NAND_MAX_OOBSIZE];
282 uint8_t databuf[NAND_MAX_PAGESIZE];
283 uint8_t oobrbuf[NAND_MAX_OOBSIZE];
284 };
285
286 /**
287 * struct nand_chip - NAND Private Flash Chip Data
288 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
289 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
290 * @read_byte: [REPLACEABLE] read one byte from the chip
291 * @read_word: [REPLACEABLE] read one word from the chip
292 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
293 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
294 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
295 * @select_chip: [REPLACEABLE] select chip nr
296 * @block_bad: [REPLACEABLE] check, if the block is bad
297 * @block_markbad: [REPLACEABLE] mark the block bad
298 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
299 * ALE/CLE/nCE. Also used to write command and address
300 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
301 * If set to NULL no access to ready/busy is available and the ready/busy information
302 * is read from the chip status register
303 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
304 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
305 * @ecc: [BOARDSPECIFIC] ecc control ctructure
306 * @buffers: buffer structure for read/write
307 * @hwcontrol: platform-specific hardware control structure
308 * @ops: oob operation operands
309 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
310 * @scan_bbt: [REPLACEABLE] function to scan bad block table
311 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
312 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
313 * @state: [INTERN] the current state of the NAND device
314 * @oob_poi: poison value buffer
315 * @page_shift: [INTERN] number of address bits in a page (column address bits)
316 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
317 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
318 * @chip_shift: [INTERN] number of address bits in one chip
319 * @datbuf: [INTERN] internal buffer for one page + oob
320 * @oobbuf: [INTERN] oob buffer for one eraseblock
321 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
322 * @data_poi: [INTERN] pointer to a data buffer
323 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
324 * special functionality. See the defines for further explanation
325 * @badblockpos: [INTERN] position of the bad block marker in the oob area
326 * @numchips: [INTERN] number of physical chips
327 * @chipsize: [INTERN] the size of one chip for multichip arrays
328 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
329 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
330 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
331 * @bbt: [INTERN] bad block table pointer
332 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
333 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
334 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
335 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
336 * which is shared among multiple independend devices
337 * @priv: [OPTIONAL] pointer to private chip date
338 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
339 * (determine if errors are correctable)
340 */
341
342 struct nand_chip {
343 void __iomem *IO_ADDR_R;
344 void __iomem *IO_ADDR_W;
345
346 uint8_t (*read_byte)(struct mtd_info *mtd);
347 u16 (*read_word)(struct mtd_info *mtd);
348 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
349 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
350 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
351 void (*select_chip)(struct mtd_info *mtd, int chip);
352 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
353 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
354 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
355 unsigned int ctrl);
356 int (*dev_ready)(struct mtd_info *mtd);
357 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
358 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
359 void (*erase_cmd)(struct mtd_info *mtd, int page);
360 int (*scan_bbt)(struct mtd_info *mtd);
361 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
362
363 int chip_delay;
364 unsigned int options;
365
366 int page_shift;
367 int phys_erase_shift;
368 int bbt_erase_shift;
369 int chip_shift;
370 int numchips;
371 unsigned long chipsize;
372 int pagemask;
373 int pagebuf;
374 int badblockpos;
375
376 nand_state_t state;
377
378 uint8_t *oob_poi;
379 struct nand_hw_control *controller;
380 struct nand_ecclayout *ecclayout;
381
382 struct nand_ecc_ctrl ecc;
383 struct nand_buffers buffers;
384 struct nand_hw_control hwcontrol;
385
386 struct mtd_oob_ops ops;
387
388 uint8_t *bbt;
389 struct nand_bbt_descr *bbt_td;
390 struct nand_bbt_descr *bbt_md;
391
392 struct nand_bbt_descr *badblock_pattern;
393
394 void *priv;
395 };
396
397 /*
398 * NAND Flash Manufacturer ID Codes
399 */
400 #define NAND_MFR_TOSHIBA 0x98
401 #define NAND_MFR_SAMSUNG 0xec
402 #define NAND_MFR_FUJITSU 0x04
403 #define NAND_MFR_NATIONAL 0x8f
404 #define NAND_MFR_RENESAS 0x07
405 #define NAND_MFR_STMICRO 0x20
406 #define NAND_MFR_HYNIX 0xad
407
408 /**
409 * struct nand_flash_dev - NAND Flash Device ID Structure
410 * @name: Identify the device type
411 * @id: device ID code
412 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
413 * If the pagesize is 0, then the real pagesize
414 * and the eraseize are determined from the
415 * extended id bytes in the chip
416 * @erasesize: Size of an erase block in the flash device.
417 * @chipsize: Total chipsize in Mega Bytes
418 * @options: Bitfield to store chip relevant options
419 */
420 struct nand_flash_dev {
421 char *name;
422 int id;
423 unsigned long pagesize;
424 unsigned long chipsize;
425 unsigned long erasesize;
426 unsigned long options;
427 };
428
429 /**
430 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
431 * @name: Manufacturer name
432 * @id: manufacturer ID code of device.
433 */
434 struct nand_manufacturers {
435 int id;
436 char * name;
437 };
438
439 extern struct nand_flash_dev nand_flash_ids[];
440 extern struct nand_manufacturers nand_manuf_ids[];
441
442 /**
443 * struct nand_bbt_descr - bad block table descriptor
444 * @options: options for this descriptor
445 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
446 * when bbt is searched, then we store the found bbts pages here.
447 * Its an array and supports up to 8 chips now
448 * @offs: offset of the pattern in the oob area of the page
449 * @veroffs: offset of the bbt version counter in the oob are of the page
450 * @version: version read from the bbt page during scan
451 * @len: length of the pattern, if 0 no pattern check is performed
452 * @maxblocks: maximum number of blocks to search for a bbt. This number of
453 * blocks is reserved at the end of the device where the tables are
454 * written.
455 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
456 * bad) block in the stored bbt
457 * @pattern: pattern to identify bad block table or factory marked good /
458 * bad blocks, can be NULL, if len = 0
459 *
460 * Descriptor for the bad block table marker and the descriptor for the
461 * pattern which identifies good and bad blocks. The assumption is made
462 * that the pattern and the version count are always located in the oob area
463 * of the first block.
464 */
465 struct nand_bbt_descr {
466 int options;
467 int pages[NAND_MAX_CHIPS];
468 int offs;
469 int veroffs;
470 uint8_t version[NAND_MAX_CHIPS];
471 int len;
472 int maxblocks;
473 int reserved_block_code;
474 uint8_t *pattern;
475 };
476
477 /* Options for the bad block table descriptors */
478
479 /* The number of bits used per block in the bbt on the device */
480 #define NAND_BBT_NRBITS_MSK 0x0000000F
481 #define NAND_BBT_1BIT 0x00000001
482 #define NAND_BBT_2BIT 0x00000002
483 #define NAND_BBT_4BIT 0x00000004
484 #define NAND_BBT_8BIT 0x00000008
485 /* The bad block table is in the last good block of the device */
486 #define NAND_BBT_LASTBLOCK 0x00000010
487 /* The bbt is at the given page, else we must scan for the bbt */
488 #define NAND_BBT_ABSPAGE 0x00000020
489 /* The bbt is at the given page, else we must scan for the bbt */
490 #define NAND_BBT_SEARCH 0x00000040
491 /* bbt is stored per chip on multichip devices */
492 #define NAND_BBT_PERCHIP 0x00000080
493 /* bbt has a version counter at offset veroffs */
494 #define NAND_BBT_VERSION 0x00000100
495 /* Create a bbt if none axists */
496 #define NAND_BBT_CREATE 0x00000200
497 /* Search good / bad pattern through all pages of a block */
498 #define NAND_BBT_SCANALLPAGES 0x00000400
499 /* Scan block empty during good / bad block scan */
500 #define NAND_BBT_SCANEMPTY 0x00000800
501 /* Write bbt if neccecary */
502 #define NAND_BBT_WRITE 0x00001000
503 /* Read and write back block contents when writing bbt */
504 #define NAND_BBT_SAVECONTENT 0x00002000
505 /* Search good / bad pattern on the first and the second page */
506 #define NAND_BBT_SCAN2NDPAGE 0x00004000
507
508 /* The maximum number of blocks to scan for a bbt */
509 #define NAND_BBT_SCAN_MAXBLOCKS 4
510
511 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
512 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
513 extern int nand_default_bbt(struct mtd_info *mtd);
514 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
515 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
516 int allowbbt);
517 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
518 size_t * retlen, uint8_t * buf);
519
520 /*
521 * Constants for oob configuration
522 */
523 #define NAND_SMALL_BADBLOCK_POS 5
524 #define NAND_LARGE_BADBLOCK_POS 0
525
526 /**
527 * struct platform_nand_chip - chip level device structure
528 * @nr_chips: max. number of chips to scan for
529 * @chip_offset: chip number offset
530 * @nr_partitions: number of partitions pointed to by partitions (or zero)
531 * @partitions: mtd partition list
532 * @chip_delay: R/B delay value in us
533 * @options: Option flags, e.g. 16bit buswidth
534 * @ecclayout: ecc layout info structure
535 * @priv: hardware controller specific settings
536 */
537 struct platform_nand_chip {
538 int nr_chips;
539 int chip_offset;
540 int nr_partitions;
541 struct mtd_partition *partitions;
542 struct nand_ecclayout *ecclayout;
543 int chip_delay;
544 unsigned int options;
545 void *priv;
546 };
547
548 /**
549 * struct platform_nand_ctrl - controller level device structure
550 * @hwcontrol: platform specific hardware control structure
551 * @dev_ready: platform specific function to read ready/busy pin
552 * @select_chip: platform specific chip select function
553 * @priv: private data to transport driver specific settings
554 *
555 * All fields are optional and depend on the hardware driver requirements
556 */
557 struct platform_nand_ctrl {
558 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
559 int (*dev_ready)(struct mtd_info *mtd);
560 void (*select_chip)(struct mtd_info *mtd, int chip);
561 void *priv;
562 };
563
564 /* Some helpers to access the data structures */
565 static inline
get_platform_nandchip(struct mtd_info * mtd)566 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
567 {
568 struct nand_chip *chip = mtd->priv;
569
570 return chip->priv;
571 }
572
573 #endif /* __LINUX_MTD_NAND_H */
574