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Searched refs:ORR (Results 1 – 9 of 9) sorted by relevance

/external/v8/src/arm/
Dconstants-arm.h138 ORR = 12, // Logical (inclusive) OR enumerator
Ddisasm-arm.cc732 case ORR: { in DecodeType01()
Dsimulator-arm.cc1622 case ORR: { in DecodeType01()
/external/webkit/JavaScriptCore/assembler/
DARMAssembler.h117 ORR = (0xc << 21), enumerator
333 emitInst(static_cast<ARMWord>(cc) | ORR, rd, rn, op2);
338 emitInst(static_cast<ARMWord>(cc) | ORR | SET_CC, rd, rn, op2);
/external/tremolo/Tremolo/
DbitwiseARM.s108 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
304 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
Ddpen.s145 ORR r0, r14,r10,LSL #8 @ r7 = chase = (next<<8) | r14
205 ORR r0, r14,r10,LSL #16 @ r7 = chase = (next<<16) | r14
DmdctARM.s1003 ORR r7, r7, r8, LSL #6 @ r7 = bitrev[bit]
DmdctLARM.s998 ORR r7, r7, r8, LSL #6 @ r7 = bitrev[bit]
/external/srec/config/en.us/dictionary/
Dc0.682337 ORR AO1 R