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Searched refs:ioaddr (Results 1 – 25 of 26) sorted by relevance

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/external/grub/netboot/
Dlance.c138 static unsigned short ioaddr; variable
218 (void)inw(ioaddr+LANCE_RESET); in lance_reset()
221 outw(0, ioaddr+LANCE_RESET); in lance_reset()
226 outw(0x2, ioaddr+LANCE_ADDR); in lance_reset()
228 outw(inw(ioaddr+LANCE_BUS_IF) | 0x2, ioaddr+LANCE_BUS_IF); in lance_reset()
237 outw(49, ioaddr+0x12) ; in lance_reset()
238 media = inw(ioaddr+0x16) ; in lance_reset()
249 outw(49, ioaddr+0x12) ; in lance_reset()
250 outw(media, ioaddr+0x16) ; in lance_reset()
251 outw(49, ioaddr+0x12) ; in lance_reset()
[all …]
Deepro.c261 #define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(40); argument
264 #define eepro_sel_reset(ioaddr) { \ argument
265 outb(SEL_RESET_CMD, ioaddr); \
271 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG) argument
274 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr) argument
277 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr) argument
280 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr) argument
281 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr) argument
282 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr) argument
288 static unsigned short ioaddr = 0; variable
[all …]
Dvia-rhine.c53 #define byPAR0 ioaddr
54 #define byRCR ioaddr + 6
55 #define byTCR ioaddr + 7
56 #define byCR0 ioaddr + 8
57 #define byCR1 ioaddr + 9
58 #define byISR0 ioaddr + 0x0c
59 #define byISR1 ioaddr + 0x0d
60 #define byIMR0 ioaddr + 0x0e
61 #define byIMR1 ioaddr + 0x0f
62 #define byMAR0 ioaddr + 0x10
[all …]
Dtiara.c109 static unsigned short ioaddr; variable
118 outb(CARD_DISABLE, ioaddr + DLCR_ENABLE); in tiara_reset()
119 outb(CLEAR_STATUS, ioaddr + DLCR_XMIT_STAT); in tiara_reset()
120 outb(NO_TX_IRQS, ioaddr + DLCR_XMIT_MASK); in tiara_reset()
121 outb(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT); in tiara_reset()
122 outb(XMIT_MODE, ioaddr + DLCR_XMIT_MODE); in tiara_reset()
123 outb(RECV_MODE, ioaddr + DLCR_RECV_MODE); in tiara_reset()
125 while ((inb(ioaddr + DLCR_RECV_MODE) & BUF_EMPTY) == 0) in tiara_reset()
126 inb(ioaddr + BMPR_MEM_PORT); in tiara_reset()
129 outb(nic->node_addr[i], ioaddr + DLCR_NODE_ID + i); in tiara_reset()
[all …]
Dtulip.c380 static u32 ioaddr; variable
480 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
573 long mdio_addr = ioaddr + CSR9; in mdio_read()
581 outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0); in mdio_read()
582 inl(ioaddr + 0xA0); in mdio_read()
583 inl(ioaddr + 0xA0); in mdio_read()
585 if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000)) in mdio_read()
593 return inl(ioaddr + 0xB4 + (location<<2)); in mdio_read()
595 return inl(ioaddr + 0xD0); in mdio_read()
597 return inl(ioaddr + 0xD4 + ((location-29)<<2)); in mdio_read()
[all …]
Dnatsemi.c194 static unsigned long ioaddr; variable
260 ioaddr = *io_addrs & ~3; in natsemi_probe()
280 prev_eedata = eeprom_read(ioaddr, 6); in natsemi_probe()
282 int eedata = eeprom_read(ioaddr, i + 7); in natsemi_probe()
289 nic->node_addr, ioaddr); in natsemi_probe()
293 outl(ChipReset, ioaddr + ChipCmd); in natsemi_probe()
297 u32 chip_config = inl(ioaddr + ChipConfig); in natsemi_probe()
306 nic_name, (int)inl(ioaddr + 0x84), advertising); in natsemi_probe()
314 SavedClkRun = inl(ioaddr + ClkRun); in natsemi_probe()
315 outl(SavedClkRun & ~0x100, ioaddr + ClkRun); in natsemi_probe()
[all …]
Di82586.c246 static unsigned short ioaddr, irq, scb_base; variable
311 outb(0, ioaddr + I82586_ATTN); in ack_status()
328 outb(0x20, ioaddr + MISC_CTRL); in i82586_reset()
345 outb(0xA0, ioaddr + MISC_CTRL); in i82586_reset()
350 outb(0, ioaddr + I82586_ATTN); in i82586_reset()
363 outb(0, ioaddr + I82586_ATTN); in i82586_reset()
367 outb(0x80, ioaddr + MISC_CTRL); in i82586_reset()
488 outb(0, ioaddr + I82586_ATTN); in i82586_disable()
490 outb(0, ioaddr + NI52_RESET); in i82586_disable()
497 static int t507_probe1(struct nic *nic, unsigned short ioaddr) in t507_probe1() argument
[all …]
Drtl8139.c158 static int ioaddr; variable
195 ioaddr = probeaddrs[0] & ~3; in rtl8139_probe()
200 outb(0x00, ioaddr + Config1); in rtl8139_probe()
209 *ap++ = inb(ioaddr + MAC0 + i); in rtl8139_probe()
212 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10; in rtl8139_probe()
213 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex; in rtl8139_probe()
214 printf("ioaddr %#hX, addr %! %sMbps %s-duplex\n", ioaddr, in rtl8139_probe()
255 long ee_addr = ioaddr + Cfg9346; in read_eeprom()
289 outb(CmdReset, ioaddr + ChipCmd); in rtl_reset()
296 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running()) in rtl_reset()
[all …]
Deepro100.c106 static int ioaddr; variable
282 ioaddr + SCBCtrlMDI); in mdio_write()
286 val = inl(ioaddr + SCBCtrlMDI); in mdio_write()
302 outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI); in mdio_read()
306 val = inl(ioaddr + SCBCtrlMDI); in mdio_read()
324 long ee_addr = ioaddr + SCBeeprom; in do_eeprom_cmd()
361 outl(0, ioaddr + SCBPort); in eepro100_reset()
385 status = inw(ioaddr + SCBStatus); in eepro100_transmit()
387 outw(status & 0xfc00, ioaddr + SCBStatus); in eepro100_transmit()
391 t, s, status, inw (ioaddr + SCBCmd)); in eepro100_transmit()
[all …]
Dotulip.c32 static unsigned short ioaddr; variable
162 outl(0x00000001, ioaddr + CSR0); in tulip_reset()
165 outl(0x01A08000, ioaddr + CSR0); in tulip_reset()
173 outl(0x32404000, ioaddr + CSR6); in tulip_reset()
175 outl(0x32000040, ioaddr + CSR6); in tulip_reset()
186 outl(0x0, ioaddr + CSR13); /* reset SIA */ in tulip_reset()
187 outl(0x7f3f, ioaddr + CSR14); in tulip_reset()
188 outl(0x8000008, ioaddr + CSR15); in tulip_reset()
189 outl(0x0, ioaddr + CSR13); in tulip_reset()
190 outl(0x1, ioaddr + CSR13); in tulip_reset()
[all …]
Dni5010.c53 #define EDLC_XSTAT (ioaddr + 0x00) /* EDLC transmit csr */
54 #define EDLC_XCLR (ioaddr + 0x00) /* EDLC transmit "Clear IRQ" */
55 #define EDLC_XMASK (ioaddr + 0x01) /* EDLC transmit "IRQ Masks" */
56 #define EDLC_RSTAT (ioaddr + 0x02) /* EDLC receive csr */
57 #define EDLC_RCLR (ioaddr + 0x02) /* EDLC receive "Clear IRQ" */
58 #define EDLC_RMASK (ioaddr + 0x03) /* EDLC receive "IRQ Masks" */
59 #define EDLC_XMODE (ioaddr + 0x04) /* EDLC transmit Mode */
60 #define EDLC_RMODE (ioaddr + 0x05) /* EDLC receive Mode */
61 #define EDLC_RESET (ioaddr + 0x06) /* EDLC RESET register */
62 #define EDLC_TDR1 (ioaddr + 0x07) /* "Time Domain Reflectometry" reg1 */
[all …]
Ddavicom.c133 static unsigned long ioaddr; variable
163 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
229 io_dcr9 = ioaddr + CSR9; in phy_read()
273 io_dcr9 = ioaddr + CSR9; in phy_write()
368 outl(csr6, ioaddr + CSR6); in davicom_media_chk()
387 outl(csr6, ioaddr + CSR6); in davicom_media_chk()
402 static int read_eeprom(unsigned long ioaddr, int location, int addr_len) in read_eeprom() argument
406 long ee_addr = ioaddr + CSR9; in read_eeprom()
496 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in davicom_reset()
499 outl(0x00000001, ioaddr + CSR0); in davicom_reset()
[all …]
Dfa311.c101 unsigned int ioaddr; member
112 static int eeprom_read(long ioaddr, int location);
139 dev->ioaddr = pci->membase; in fa311_probe()
142 prev_eedata = eeprom_read(dev->ioaddr, 6); in fa311_probe()
144 int eedata = eeprom_read(dev->ioaddr, i + 7); in fa311_probe()
169 writel(virt_to_bus(dev->rx_ring), dev->ioaddr + RxRingPtr); in fa311_probe()
170 writel(virt_to_bus(dev->tx_ring), dev->ioaddr + TxRingPtr); in fa311_probe()
174 writel(i, dev->ioaddr + RxFilterAddr); in fa311_probe()
176 dev->ioaddr + RxFilterData); in fa311_probe()
181 if (readl(dev->ioaddr + ChipConfig) & 0x20000000) in fa311_probe()
[all …]
Dsmc9000.c70 static void smc_reset(int ioaddr) in smc_reset() argument
74 SMC_SELECT_BANK(ioaddr, 0); in smc_reset()
75 _outw( RCR_SOFTRESET, ioaddr + RCR ); in smc_reset()
78 SMC_DELAY(ioaddr); in smc_reset()
82 _outw(RCR_CLEAR, ioaddr + RCR); in smc_reset()
83 _outw(TCR_CLEAR, ioaddr + TCR); in smc_reset()
86 SMC_SELECT_BANK(ioaddr, 2); in smc_reset()
87 _outw( MC_RESET, ioaddr + MMU_CMD ); in smc_reset()
92 _outb(0, ioaddr + INT_MASK); in smc_reset()
110 static int smc_probe( int ioaddr ) in smc_probe() argument
[all …]
Dsis900.c53 static unsigned long ioaddr; variable
231 ioaddr = *io_addrs & ~3; in sis900_probe()
257 nic->node_addr, ioaddr); in sis900_probe()
342 long ee_addr = ioaddr + mear; in sis900_read_eeprom()
411 long mdio_addr = ioaddr + mear; in sis900_mdio_read()
440 long mdio_addr = ioaddr + mear; in sis900_mdio_write()
503 outl(RxENA, ioaddr + cr); in sis900_init()
523 outl(0, ioaddr + ier); in sis900_reset()
524 outl(0, ioaddr + imr); in sis900_reset()
525 outl(0, ioaddr + rfcr); in sis900_reset()
[all …]
D3c90x.c256 a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param) in a3c90x_internal_IssueCommand() argument
266 outw(val, ioaddr + regCommandIntStatus_w); in a3c90x_internal_IssueCommand()
269 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS); in a3c90x_internal_IssueCommand()
278 a3c90x_internal_SetWindow(int ioaddr, int window) in a3c90x_internal_SetWindow() argument
285 a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window); in a3c90x_internal_SetWindow()
295 a3c90x_internal_ReadEeprom(int ioaddr, int address) in a3c90x_internal_ReadEeprom() argument
303 while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); in a3c90x_internal_ReadEeprom()
306 outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w); in a3c90x_internal_ReadEeprom()
307 while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); in a3c90x_internal_ReadEeprom()
308 val = inw(ioaddr + regEepromData_0_w); in a3c90x_internal_ReadEeprom()
[all …]
Dw89c840.c261 static int ioaddr; variable
272 static int eeprom_read(long ioaddr, int location);
323 writel(0x00000001, ioaddr + PCIBusCfg); in w89c840_reset()
327 writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr); in w89c840_reset()
328 writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr); in w89c840_reset()
331 writeb(nic->node_addr[i], ioaddr + StationAddr + i); in w89c840_reset()
345 writel(0xE010, ioaddr + PCIBusCfg); in w89c840_reset()
347 writel(0, ioaddr + RxStartDemand); in w89c840_reset()
353 writel(0x1A0F5, ioaddr + IntrStatus); in w89c840_reset()
354 writel(0x1A0F5, ioaddr + IntrEnable); in w89c840_reset()
[all …]
Depic100.c61 static int ioaddr; variable
121 ioaddr = probeaddrs[0] & ~3; /* Mask the bit that says "this is an io addr" */ in epic100_probe()
124 command = ioaddr + COMMAND; /* Control Register */ in epic100_probe()
125 intstat = ioaddr + INTSTAT; /* Interrupt Status */ in epic100_probe()
126 intmask = ioaddr + INTMASK; /* Interrupt Mask */ in epic100_probe()
127 genctl = ioaddr + GENCTL; /* General Control */ in epic100_probe()
128 eectl = ioaddr + EECTL; /* EEPROM Control */ in epic100_probe()
129 test = ioaddr + TEST; /* Test register (clocks) */ in epic100_probe()
130 mmctl = ioaddr + MMCTL; /* MII Management Interface Control */ in epic100_probe()
131 mmdata = ioaddr + MMDATA; /* MII Management Interface Data */ in epic100_probe()
[all …]
Ddepca.c239 #define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */
240 #define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */
241 #define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */
242 #define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */
243 #define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */
244 #define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */
245 #define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */
246 #define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */
464 static unsigned short ioaddr = 0; variable
721 adapter_name[adapter], ioaddr, mem_start, mem_start + mem_len, in depca_probe1()
[all …]
Dsk_g16.c142 #define SK_POS0 ioaddr /* Card-ID Low (R) */
143 #define SK_POS1 ioaddr+1 /* Card-ID High (R) */
144 #define SK_POS2 ioaddr+2 /* Card-Enable, Boot-ROM Disable (RW) */
145 #define SK_POS3 ioaddr+3 /* Base address of RAM */
146 #define SK_POS4 ioaddr+4 /* IRQ */
451 static unsigned short ioaddr; /* base io address */ variable
753 for (p = probe_addrs; (ioaddr = *p) != 0; ++p) in SK_probe()
755 long offset1, offset0 = inb(ioaddr); in SK_probe()
757 ((offset1 = inb(ioaddr + 1)) == SK_IDHIGH)) in SK_probe()
758 if (SK_probe1(nic, ioaddr) >= 0) in SK_probe()
[all …]
Dpci.c404 unsigned int membase, ioaddr, romaddr; in scan_bus() local
441 pcibios_read_config_dword(bus, devfn, reg, &ioaddr); in scan_bus()
443 if ((ioaddr & PCI_BASE_ADDRESS_IO_MASK) == 0 || (ioaddr & PCI_BASE_ADDRESS_SPACE_IO) == 0) in scan_bus()
446 ioaddr &= PCI_BASE_ADDRESS_IO_MASK; in scan_bus()
454 pcidev[i].name, ioaddr, romaddr); in scan_bus()
458 pcidev[i].ioaddr = ioaddr; in scan_bus()
Dcs89x0.c456 unsigned rev_type = 0, ioaddr, ioidx, isa_cnf, cs_revision; in cs89x0_probe() local
460 for (ioidx = 0; (ioaddr=netcard_portlist[ioidx++]) != 0; ) { in cs89x0_probe()
464 if (ioaddr & 1) { in cs89x0_probe()
465 ioaddr &= ~1; in cs89x0_probe()
466 if ((inw(ioaddr + ADD_PORT) & ADD_MASK) != ADD_SIG) in cs89x0_probe()
468 outw(PP_ChipID, ioaddr + ADD_PORT); in cs89x0_probe()
471 if (inw(ioaddr + DATA_PORT) != CHIP_EISA_ID_SIG) in cs89x0_probe()
473 eth_nic_base = ioaddr; in cs89x0_probe()
645 if (ioaddr == 0) in cs89x0_probe()
Dtlan.c1775 static int TLan_probe1( struct pci_dev *pdev, long ioaddr, int irq, int rev, const struct pci_…
1978 long ioaddr, int irq, int rev, const struct pci_device_id *ent )
2031 device_id = inw(ioaddr + EISA_ID2);
2040 dev->base_addr = ioaddr;
2152 long ioaddr;
2163 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
2165 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC80, inw(ioaddr + EISA_ID));
2166 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC82, inw(ioaddr + EISA_ID2));
2169 (int) ioaddr);
2170 if (request_region(ioaddr, 0x10, TLanSignature) == NULL)
[all …]
Dconfig.c531 if (p->ioaddr != 0) in eth_probe()
533 pci_ioaddrs[0] = p->ioaddr; in eth_probe()
Dpci.h178 unsigned short ioaddr; member

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