72 	outw(RX_DISABLE, BASE + EP_COMMAND);  in t509_reset()
73 	outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);  in t509_reset()
74 	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)  in t509_reset()
76 	outw(TX_DISABLE, BASE + EP_COMMAND);  in t509_reset()
77 	outw(STOP_TRANSCEIVER, BASE + EP_COMMAND);  in t509_reset()
79 	outw(RX_RESET, BASE + EP_COMMAND);  in t509_reset()
80 	outw(TX_RESET, BASE + EP_COMMAND);  in t509_reset()
81 	outw(C_INTR_LATCH, BASE + EP_COMMAND);  in t509_reset()
82 	outw(SET_RD_0_MASK, BASE + EP_COMMAND);  in t509_reset()
83 	outw(SET_INTR_MASK, BASE + EP_COMMAND);  in t509_reset()
84 	outw(SET_RX_FILTER, BASE + EP_COMMAND);  in t509_reset()
89 	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)  in t509_reset()
95 	outw(0, BASE + EP_W0_CONFIG_CTRL);  in t509_reset()
98 	outw(SET_IRQ(0), BASE + EP_W0_RESOURCE_CFG);  in t509_reset()
101 	outw(ENABLE_DRQ_IRQ, BASE + EP_W0_CONFIG_CTRL);  in t509_reset()
107 		outb(nic->node_addr[i], BASE + EP_W2_ADDR_0 + i);  in t509_reset()
109 	outw(RX_RESET, BASE + EP_COMMAND);  in t509_reset()
110 	outw(TX_RESET, BASE + EP_COMMAND);  in t509_reset()
115 		inb(BASE + EP_W1_TX_STATUS);  in t509_reset()
118 	outw(ACK_INTR | 0xff, BASE + EP_COMMAND);  in t509_reset()
120 	outw(SET_RD_0_MASK | S_5_INTS, BASE + EP_COMMAND);  in t509_reset()
122 	outw(SET_INTR_MASK, BASE + EP_COMMAND);  in t509_reset()
124 	outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + EP_COMMAND);  in t509_reset()
128 		outw(START_TRANSCEIVER, BASE + EP_COMMAND);  in t509_reset()
134 		outw(ENABLE_UTP, BASE + EP_W4_MEDIA_TYPE);  in t509_reset()
140 	outw(RX_ENABLE, BASE + EP_COMMAND);  in t509_reset()
141 	outw(TX_ENABLE, BASE + EP_COMMAND);  in t509_reset()
144 	outw(SET_RX_EARLY_THRESH | ETH_ZLEN, BASE + EP_COMMAND);  in t509_reset()
145 	outw(SET_TX_START_THRESH | 16, BASE + EP_COMMAND);  in t509_reset()
185 	while ((status=inb(BASE + EP_W1_TX_STATUS)) & TXS_COMPLETE ) {  in t509_transmit()
187 			outw(TX_RESET, BASE + EP_COMMAND);  in t509_transmit()
188 			outw(TX_ENABLE, BASE + EP_COMMAND);  in t509_transmit()
190 		outb(0x0, BASE + EP_W1_TX_STATUS);  in t509_transmit()
193 	while (inw(BASE + EP_W1_FREE_TX) < (unsigned short)len + pad + 4)  in t509_transmit()
196 	outw(len, BASE + EP_W1_TX_PIO_WR_1);  in t509_transmit()
197 	outw(0x0, BASE + EP_W1_TX_PIO_WR_1);	/* Second dword meaningless */  in t509_transmit()
200 	outsw(BASE + EP_W1_TX_PIO_WR_1, d, ETH_ALEN/2);  in t509_transmit()
201 	outsw(BASE + EP_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2);  in t509_transmit()
202 	outw(t, BASE + EP_W1_TX_PIO_WR_1);  in t509_transmit()
203 	outsw(BASE + EP_W1_TX_PIO_WR_1, p, s / 2);  in t509_transmit()
205 		outb(*(p+s - 1), BASE + EP_W1_TX_PIO_WR_1);  in t509_transmit()
208 		outb(0, BASE + EP_W1_TX_PIO_WR_1);	/* Padding */  in t509_transmit()
211 	while((inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS) != 0)  in t509_transmit()
226 	cst=inw(BASE + EP_STATUS);  in t509_poll()
235 		outw(ACK_INTR| (cst & S_5_INTS), BASE + EP_COMMAND);  in t509_poll()
236 		outw(C_INTR_LATCH, BASE + EP_COMMAND);  in t509_poll()
241 	status = inw(BASE + EP_W1_RX_STATUS);  in t509_poll()
247 		outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);  in t509_poll()
259 	insw(BASE + EP_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2);  in t509_poll()
261 		nic->packet[rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1);  in t509_poll()
265 		status = inw(BASE + EP_W1_RX_STATUS);  in t509_poll()
271 			insw(BASE + EP_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2);  in t509_poll()
273 				nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1);  in t509_poll()
288 	outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);  in t509_poll()
289 	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)  in t509_poll()
601 		outw(ntohs(p[i]), BASE + EP_W2_ADDR_0 + (i * 2));  in t529_probe()