94     SibValueInfo(unsigned Reg, VNInfo *VNI)  in SibValueInfo()
95       : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}  in SibValueInfo()
130   bool isRegToSpill(unsigned Reg) {  in isRegToSpill()  argument
132                      RegsToSpill.end(), Reg) != RegsToSpill.end();  in isRegToSpill()
135   bool isSibling(unsigned Reg);
146   bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
155   void spillAroundUses(unsigned Reg);
182 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {  in isFullCopyOf()  argument
185   if (MI->getOperand(0).getReg() == Reg)  in isFullCopyOf()
187   if (MI->getOperand(1).getReg() == Reg)  in isFullCopyOf()
196   unsigned Reg = Edit->getReg();  in isSnippet()  local
216     if (isFullCopyOf(MI, Reg))  in isSnippet()
239   unsigned Reg = Edit->getReg();  in collectRegsToSpill()  local
242   RegsToSpill.assign(1, Reg);  in collectRegsToSpill()
247   if (Original == Reg)  in collectRegsToSpill()
250   for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);  in collectRegsToSpill()
252     unsigned SnipReg = isFullCopyOf(MI, Reg);  in collectRegsToSpill()
280 bool InlineSpiller::isSibling(unsigned Reg) {  in isSibling()  argument
281   return TargetRegisterInfo::isVirtualRegister(Reg) &&  in isSibling()
282            VRM.getOriginal(Reg) == Original;  in isSibling()
311     unsigned Reg;  in traceSiblingValue()  local
313     tie(Reg, VNI) = WorkList.pop_back_val();  in traceSiblingValue()
318     if (!isRegToSpill(Reg)) {  in traceSiblingValue()
338                        << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def  in traceSiblingValue()
340           SVI.SpillReg = Reg;  in traceSiblingValue()
348           DEBUG(dbgs() << "  spill depth " << Depth << ": " << PrintReg(Reg)  in traceSiblingValue()
350           SVI.SpillReg = Reg;  in traceSiblingValue()
361         DEBUG(dbgs() << "  orig phi value " << PrintReg(Reg) << ':'  in traceSiblingValue()
367       LiveInterval &LI = LIS.getInterval(Reg);  in traceSiblingValue()
373           WorkList.push_back(std::make_pair(Reg, PVNI));  in traceSiblingValue()
382     if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {  in traceSiblingValue()
396     if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {  in traceSiblingValue()
397       DEBUG(dbgs() << "  reload " << PrintReg(Reg) << ':'  in traceSiblingValue()
410     DEBUG(dbgs() << "  def " << PrintReg(Reg) << ':'  in traceSiblingValue()
442     unsigned Reg = RegsToSpill[i];  in analyzeSiblingValues()  local
443     LiveInterval &LI = LIS.getInterval(Reg);  in analyzeSiblingValues()
455           DefMI = traceSiblingValue(Reg, VNI, OrigVNI);  in analyzeSiblingValues()
460         DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'  in analyzeSiblingValues()
552     unsigned Reg = LI->reg;  in eliminateRedundantSpills()  local
557     if (isRegToSpill(Reg))  in eliminateRedundantSpills()
565     for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);  in eliminateRedundantSpills()
574       if (unsigned DstReg = isFullCopyOf(MI, Reg)) {  in eliminateRedundantSpills()
587       if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {  in eliminateRedundantSpills()
731     unsigned Reg = RegsToSpill[i];  in reMaterializeAll()  local
732     LiveInterval &LI = LIS.getInterval(Reg);  in reMaterializeAll()
734          RI = MRI.use_nodbg_begin(Reg);  in reMaterializeAll()
743     unsigned Reg = RegsToSpill[i];  in reMaterializeAll()  local
744     LiveInterval &LI = LIS.getInterval(Reg);  in reMaterializeAll()
751       MI->addRegisterDead(Reg, &TRI);  in reMaterializeAll()
768     unsigned Reg = RegsToSpill[i-1];  in reMaterializeAll()  local
769     if (!LIS.hasInterval(Reg)) {  in reMaterializeAll()
773     LiveInterval &LI = LIS.getInterval(Reg);  in reMaterializeAll()
776     Edit->eraseVirtReg(Reg, LIS);  in reMaterializeAll()
788 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {  in coalesceStackAccess()  argument
796   if (InstrReg != Reg || FI != StackSlot)  in coalesceStackAccess()
879 void InlineSpiller::spillAroundUses(unsigned Reg) {  in spillAroundUses()  argument
880   DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');  in spillAroundUses()
881   LiveInterval &OldLI = LIS.getInterval(Reg);  in spillAroundUses()
884   for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);  in spillAroundUses()
910     if (coalesceStackAccess(MI, Reg))  in spillAroundUses()
916     tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);  in spillAroundUses()
926     unsigned SibReg = isFullCopyOf(MI, Reg);  in spillAroundUses()
956     LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM);  in spillAroundUses()