53   assert(isReg() && "Can only add reg operand to use lists");  in AddRegOperandToRegInfo()
144   if (isReg() && getParent() && getParent()->getParent() &&  in ChangeToImmediate()
160   if (isReg()) {  in ChangeToRegister()
569     assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&  in ~MachineInstr()
589     if (Operands[i].isReg())  in RemoveRegOperandsFromUseLists()
599     if (Operands[i].isReg())  in AddRegOperandsToUseLists()
610   bool isImpReg = Op.isReg() && Op.isImplicit();  in addOperand()
628       if (Op.isReg()) {  in addOperand()
651     if (Operands[OpNo].isReg()) {  in addOperand()
668       assert(Operands[i].isReg() && "Should only be an implicit reg!");  in addOperand()
676     if (Operands[OpNo].isReg()) {  in addOperand()
685       assert(Operands[i].isReg() && "Should only be an implicit reg!");  in addOperand()
701     if (Operands[OpNo].isReg()  in addOperand()
716     if (Operands.back().isReg() && Operands.back().isOnRegUseList())  in RemoveOperand()
729       if (Operands[i].isReg())  in RemoveOperand()
738       if (Operands[i].isReg())  in RemoveOperand()
775     if (!MO.isReg()) {  in isIdenticalTo()
848     if (!MO.isReg() || !MO.isImplicit())  in getNumExplicitOperands()
870     if (!MO.isReg() || !MO.isUse())  in findRegisterUseOperandIdx()
898     if (!MO.isReg() || MO.getReg() != Reg)  in readsWritesVirtualRegister()
923     if (!MO.isReg() || !MO.isDef())  in findRegisterDefOperandIdx()
963     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)  in isRegTiedToUseOperand()
989       if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())  in isRegTiedToUseOperand()
1006     if (MO.isReg() && MO.isUse() &&  in isRegTiedToUseOperand()
1023     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)  in isRegTiedToDefOperand()
1067   if (!MO.isReg() || !MO.isUse())  in isRegTiedToDefOperand()
1082     if (MO.isReg() && MO.isUse())  in clearKillInfo()
1092     if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))  in copyKillDeadInfo()
1129       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1136       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1183     if (!MO.isReg())  in isSafeToReMat()
1298     if (!MO.isReg() || MO.isUse())  in allDefsAreDead()
1312     if (MO.isReg() && MO.isImplicit())  in copyImplicitOps()
1360   for (; StartOp < e && getOperand(StartOp).isReg() &&  in print()
1403     if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))  in print()
1411         MO.isReg() && MO.isImplicit() && MO.isDef()) {  in print()
1537     if (!MO.isReg() || !MO.isUse() || MO.isUndef())  in addRegisterKilled()
1595     if (!MO.isReg() || !MO.isDef())  in addRegisterDead()
1648       if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&  in addRegisterDefined()
1662     if (!MO.isReg() || !MO.isDef()) continue;  in setPhysRegsDeadExcept()