Lines Matching refs:Reg
157 void AddToLiveIns(unsigned Reg);
173 bool HasAnyPHIUse(unsigned Reg) const;
179 unsigned Reg) const;
375 unsigned Reg = MO.getReg(); in ProcessMI() local
376 if (!Reg) in ProcessMI()
378 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && in ProcessMI()
382 if (Reg && PhysRegDefs[Reg]) in ProcessMI()
390 ++PhysRegDefs[Reg]; in ProcessMI()
391 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) in ProcessMI()
406 Def = Reg; in ProcessMI()
410 if (++PhysRegDefs[Reg] > 1) in ProcessMI()
414 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) in ProcessMI()
449 unsigned Reg = *I; in HoistRegionPostRA() local
450 ++PhysRegDefs[Reg]; in HoistRegionPostRA()
451 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) in HoistRegionPostRA()
496 void MachineLICM::AddToLiveIns(unsigned Reg) { in AddToLiveIns() argument
500 if (!BB->isLiveIn(Reg)) in AddToLiveIns()
501 BB->addLiveIn(Reg); in AddToLiveIns()
508 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg())) in AddToLiveIns()
623 unsigned Reg = MO.getReg(); in InitRegPressure() local
624 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in InitRegPressure()
627 bool isNew = RegSeen.insert(Reg); in InitRegPressure()
628 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in InitRegPressure()
656 unsigned Reg = MO.getReg(); in UpdateRegPressure() local
657 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in UpdateRegPressure()
660 bool isNew = RegSeen.insert(Reg); in UpdateRegPressure()
662 Defs.push_back(Reg); in UpdateRegPressure()
664 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in UpdateRegPressure()
677 unsigned Reg = Defs.pop_back_val(); in UpdateRegPressure() local
678 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in UpdateRegPressure()
714 unsigned Reg = MO.getReg(); in IsLoopInvariantInst() local
715 if (Reg == 0) continue; in IsLoopInvariantInst()
718 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in IsLoopInvariantInst()
723 if (!MRI->def_empty(Reg)) in IsLoopInvariantInst()
725 if (AllocatableSet.test(Reg)) in IsLoopInvariantInst()
728 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in IsLoopInvariantInst()
740 } else if (CurLoop->getHeader()->isLiveIn(Reg)) { in IsLoopInvariantInst()
750 assert(MRI->getVRegDef(Reg) && in IsLoopInvariantInst()
755 if (CurLoop->contains(MRI->getVRegDef(Reg))) in IsLoopInvariantInst()
766 bool MachineLICM::HasAnyPHIUse(unsigned Reg) const { in HasAnyPHIUse()
767 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), in HasAnyPHIUse()
787 unsigned DefIdx, unsigned Reg) const { in HasHighOperandLatency()
788 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg)) in HasHighOperandLatency()
791 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), in HasHighOperandLatency()
803 if (MOReg != Reg) in HasHighOperandLatency()
832 unsigned Reg = DefMO.getReg(); in IsCheapInstruction() local
833 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in IsCheapInstruction()
878 unsigned Reg = MO.getReg(); in UpdateBackTraceRegPressure() local
879 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in UpdateBackTraceRegPressure()
882 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in UpdateBackTraceRegPressure()
941 unsigned Reg = MO.getReg(); in IsProfitableToHoist() local
942 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in IsProfitableToHoist()
945 if (HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist()
950 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in IsProfitableToHoist()
963 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in IsProfitableToHoist()
1025 unsigned Reg = MRI->createVirtualRegister(RC); in ExtractHoistableLoad() local
1030 TII->unfoldMemoryOperand(MF, MI, Reg, in ExtractHoistableLoad()