Lines Matching refs:Reg
45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
46 VRegInfo[Reg].first = RC; in setRegClass()
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
52 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
59 setRegClass(Reg, NewRC); in constrainRegClass()
73 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
78 VRegInfo.grow(Reg); in createVirtualRegister()
79 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
80 RegAllocHints.grow(Reg); in createVirtualRegister()
85 return Reg; in createVirtualRegister()
95 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in HandleVRegListReallocation() local
96 MachineOperand *List = VRegInfo[Reg].second; in HandleVRegListReallocation()
99 List->Contents.Reg.Prev = &VRegInfo[Reg].second; in HandleVRegListReallocation()
121 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { in getVRegDef()
123 if (!def_empty(Reg)) in getVRegDef()
124 return &*def_begin(Reg); in getVRegDef()
146 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { in clearKillFlags()
147 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) in clearKillFlags()
151 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { in isLiveIn()
153 if (I->first == Reg || I->second == Reg) in isLiveIn()
158 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { in isLiveOut()
160 if (*I == Reg) in isLiveOut()
225 void MachineRegisterInfo::dumpUses(unsigned Reg) const { in dumpUses()
226 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) in dumpUses()