83     void addRegWithSubRegs(RegVector &RV, unsigned Reg) {  in addRegWithSubRegs()
84       RV.push_back(Reg);  in addRegWithSubRegs()
85       if (TargetRegisterInfo::isPhysicalRegister(Reg))  in addRegWithSubRegs()
86         for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)  in addRegWithSubRegs()
118       bool addPassed(unsigned Reg) {  in addPassed()
119         if (!TargetRegisterInfo::isVirtualRegister(Reg))  in addPassed()
121         if (regsKilled.count(Reg) || regsLiveOut.count(Reg))  in addPassed()
123         return vregsPassed.insert(Reg).second;  in addPassed()
137       bool addRequired(unsigned Reg) {  in addRequired()
138         if (!TargetRegisterInfo::isVirtualRegister(Reg))  in addRequired()
140         if (regsLiveOut.count(Reg))  in addRequired()
142         return vregsRequired.insert(Reg).second;  in addRequired()
164       bool isLiveOut(unsigned Reg) const {  in isLiveOut()
165         return regsLiveOut.count(Reg) || vregsPassed.count(Reg);  in isLiveOut()
172     bool isReserved(unsigned Reg) {  in isReserved()
173       return Reg < regsReserved.size() && regsReserved.test(Reg);  in isReserved()
369   for (int Reg = regsReserved.find_first(); Reg>=0;  in visitMachineFunctionBefore()  local
370        Reg = regsReserved.find_next(Reg)) {  in visitMachineFunctionBefore()
371     for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {  in visitMachineFunctionBefore()
607     const unsigned Reg = MO->getReg();  in visitMachineOperand()  local
608     if (!Reg)  in visitMachineOperand()
615       regsLiveInButUnused.erase(Reg);  in visitMachineOperand()
622         if (Reg == DefReg)  in visitMachineOperand()
624         else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {  in visitMachineOperand()
632         addRegWithSubRegs(regsKilled, Reg);  in visitMachineOperand()
635       if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&  in visitMachineOperand()
637         LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);  in visitMachineOperand()
644       if (TargetRegisterInfo::isVirtualRegister(Reg) &&  in visitMachineOperand()
647         if (LiveInts->hasInterval(Reg)) {  in visitMachineOperand()
648           const LiveInterval &LI = LiveInts->getInterval(Reg);  in visitMachineOperand()
665       if (!regsLive.count(Reg)) {  in visitMachineOperand()
666         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {  in visitMachineOperand()
668           if (!isReserved(Reg))  in visitMachineOperand()
675           if (MInfo.regsKilled.count(Reg))  in visitMachineOperand()
678             MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));  in visitMachineOperand()
685         addRegWithSubRegs(regsDead, Reg);  in visitMachineOperand()
687         addRegWithSubRegs(regsDefined, Reg);  in visitMachineOperand()
690       if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&  in visitMachineOperand()
693         if (LiveInts->hasInterval(Reg)) {  in visitMachineOperand()
694           const LiveInterval &LI = LiveInts->getInterval(Reg);  in visitMachineOperand()
716       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {  in visitMachineOperand()
717         unsigned sr = Reg;  in visitMachineOperand()
719           unsigned s = TRI->getSubReg(Reg, SubIdx);  in visitMachineOperand()
736         const TargetRegisterClass *RC = MRI->getRegClass(Reg);  in visitMachineOperand()
899       unsigned Reg = BBI->getOperand(i).getReg();  in checkPHIOps()  local
905       if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))  in checkPHIOps()
948     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);  in verifyLiveVariables()  local
949     LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);  in verifyLiveVariables()
955       if (MInfo.vregsRequired.count(Reg)) {  in verifyLiveVariables()
958           *OS << "Virtual register " << PrintReg(Reg)  in verifyLiveVariables()
964           *OS << "Virtual register " << PrintReg(Reg)  in verifyLiveVariables()