656     unsigned Reg = MO.getReg();  in handleThroughOperands()  local
657     if (!TargetRegisterInfo::isVirtualRegister(Reg))  in handleThroughOperands()
660         (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {  in handleThroughOperands()
661       if (ThroughRegs.insert(Reg))  in handleThroughOperands()
662         DEBUG(dbgs() << ' ' << PrintReg(Reg));  in handleThroughOperands()
672     unsigned Reg = MO.getReg();  in handleThroughOperands()  local
673     if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;  in handleThroughOperands()
674     UsedInInstr.set(Reg);  in handleThroughOperands()
675     if (ThroughRegs.count(PhysRegState[Reg]))  in handleThroughOperands()
676       definePhysReg(MI, Reg, regFree);  in handleThroughOperands()
677     for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {  in handleThroughOperands()
689     unsigned Reg = MO.getReg();  in handleThroughOperands()  local
690     if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;  in handleThroughOperands()
696       LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);  in handleThroughOperands()
701     } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {  in handleThroughOperands()
705       LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);  in handleThroughOperands()
709       LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);  in handleThroughOperands()
712         VirtDead.push_back(Reg);  in handleThroughOperands()
721     unsigned Reg = MO.getReg();  in handleThroughOperands()  local
722     if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;  in handleThroughOperands()
723     DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)  in handleThroughOperands()
725     UsedInInstr.set(Reg);  in handleThroughOperands()
777         for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {  in AllocateBasicBlock()
778           if (PhysRegState[Reg] == regDisabled) continue;  in AllocateBasicBlock()
779           dbgs() << " " << TRI->getName(Reg);  in AllocateBasicBlock()
780           switch(PhysRegState[Reg]) {  in AllocateBasicBlock()
787             dbgs() << '=' << PrintReg(PhysRegState[Reg]);  in AllocateBasicBlock()
788             if (LiveVirtRegs[PhysRegState[Reg]].Dirty)  in AllocateBasicBlock()
790             assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&  in AllocateBasicBlock()
816           unsigned Reg = MO.getReg();  in AllocateBasicBlock()  local
817           if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;  in AllocateBasicBlock()
818           LiveDbgValueMap[Reg].push_back(MI);  in AllocateBasicBlock()
819           LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);  in AllocateBasicBlock()
823             int SS = StackSlotForVirtReg[Reg];  in AllocateBasicBlock()
881       unsigned Reg = MO.getReg();  in AllocateBasicBlock()  local
882       if (!Reg) continue;  in AllocateBasicBlock()
883       if (TargetRegisterInfo::isVirtualRegister(Reg)) {  in AllocateBasicBlock()
891           if (MO.getSubReg() && MI->readsVirtualRegister(Reg))  in AllocateBasicBlock()
896       if (!RegClassInfo.isAllocatable(Reg)) continue;  in AllocateBasicBlock()
900         definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?  in AllocateBasicBlock()
931       unsigned Reg = MO.getReg();  in AllocateBasicBlock()  local
932       if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;  in AllocateBasicBlock()
934         LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);  in AllocateBasicBlock()
936         CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;  in AllocateBasicBlock()
951         unsigned Reg = MO.getReg();  in AllocateBasicBlock()  local
952         if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;  in AllocateBasicBlock()
955         UsedInInstr.set(Reg);  in AllocateBasicBlock()
956         for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)  in AllocateBasicBlock()
982       unsigned Reg = MO.getReg();  in AllocateBasicBlock()  local
984       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {  in AllocateBasicBlock()
985         if (!RegClassInfo.isAllocatable(Reg)) continue;  in AllocateBasicBlock()
986         definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?  in AllocateBasicBlock()
990       LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);  in AllocateBasicBlock()
993         VirtDead.push_back(Reg);  in AllocateBasicBlock()
996         CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;  in AllocateBasicBlock()