Lines Matching refs:Order
1160 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); in assignRegOrStackSlotAtInterval() local
1162 for (unsigned i = 0; i != Order.size(); ++i) { in assignRegOrStackSlotAtInterval()
1163 unsigned reg = Order[i]; in assignRegOrStackSlotAtInterval()
1173 for (unsigned i = 0; i != Order.size(); ++i) { in assignRegOrStackSlotAtInterval()
1174 unsigned reg = Order[i]; in assignRegOrStackSlotAtInterval()
1434 ArrayRef<unsigned> Order; in getFreePhysReg() local
1436 Order = tri_->getRawAllocationOrder(RC, Hint.first, physReg, *mf_); in getFreePhysReg()
1438 Order = RegClassInfo.getOrder(RC); in getFreePhysReg()
1440 assert(!Order.empty() && "No allocatable register in this register class!"); in getFreePhysReg()
1443 for (unsigned i = 0; i != Order.size(); ++i) { in getFreePhysReg()
1444 unsigned Reg = Order[i]; in getFreePhysReg()
1474 for (unsigned i = 0; i != Order.size(); ++i) { in getFreePhysReg()
1475 unsigned Reg = Order[i]; in getFreePhysReg()