257     void DowngradeRegister(LiveInterval *li, unsigned Reg);
260     void UpgradeRegister(unsigned Reg);
286     unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
448 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {  in attemptTrivialCoalescing()  argument
450   if ((Preference && Preference == Reg) || !cur.containsOneValue())  in attemptTrivialCoalescing()
451     return Reg;  in attemptTrivialCoalescing()
455     return Reg;  in attemptTrivialCoalescing()
461     return Reg;  in attemptTrivialCoalescing()
475       return Reg;  in attemptTrivialCoalescing()
479       return Reg;  in attemptTrivialCoalescing()
484       return Reg;  in attemptTrivialCoalescing()
487   if (Reg == CandReg)  in attemptTrivialCoalescing()
488     return Reg;  in attemptTrivialCoalescing()
492     return Reg;  in attemptTrivialCoalescing()
495     return Reg;  in attemptTrivialCoalescing()
648     unsigned Reg = 0;  in linearScan()  local
651       Reg = cur.reg;  in linearScan()
653       Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));  in linearScan()
654     if (!Reg)  in linearScan()
666             assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&  in linearScan()
668             LiveInMBBs[i]->addLiveIn(Reg);  in linearScan()
826 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,  in getConflictWeight()  argument
830   for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),  in getConflictWeight()
864     unsigned Reg = i->first->reg;  in findIntervalsToSpill()  local
865     unsigned PhysReg = vrm_->getPhys(Reg);  in findIntervalsToSpill()
872           Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);  in findIntervalsToSpill()
879     unsigned Reg = i->first->reg;  in findIntervalsToSpill()  local
880     unsigned PhysReg = vrm_->getPhys(Reg);  in findIntervalsToSpill()
887           Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);  in findIntervalsToSpill()
939 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {  in DowngradeRegister()  argument
940   for (const unsigned *AS = tri_->getOverlaps(Reg); *AS; ++AS) {  in DowngradeRegister()
949 void RALinScan::UpgradeRegister(unsigned Reg) {  in UpgradeRegister()  argument
950   if (Reg) {  in UpgradeRegister()
951     DowngradedRegs.erase(Reg);  in UpgradeRegister()
952     for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)  in UpgradeRegister()
1002         unsigned Reg = 0;  in assignRegOrStackSlotAtInterval()  local
1004           Reg = SrcReg;  in assignRegOrStackSlotAtInterval()
1006           Reg = vrm_->getPhys(SrcReg);  in assignRegOrStackSlotAtInterval()
1007         if (Reg) {  in assignRegOrStackSlotAtInterval()
1009             Reg = tri_->getSubReg(Reg, SrcSubReg);  in assignRegOrStackSlotAtInterval()
1011             Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);  in assignRegOrStackSlotAtInterval()
1012           if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))  in assignRegOrStackSlotAtInterval()
1013             mri_->setRegAllocationHint(cur->reg, 0, Reg);  in assignRegOrStackSlotAtInterval()
1023     unsigned Reg = i->first->reg;  in assignRegOrStackSlotAtInterval()  local
1024     assert(TargetRegisterInfo::isVirtualRegister(Reg) &&  in assignRegOrStackSlotAtInterval()
1026     const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);  in assignRegOrStackSlotAtInterval()
1031       Reg = vrm_->getPhys(Reg);  in assignRegOrStackSlotAtInterval()
1032       addRegUse(Reg);  in assignRegOrStackSlotAtInterval()
1033       SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));  in assignRegOrStackSlotAtInterval()
1444     unsigned Reg = Order[i];  in getFreePhysReg()  local
1446     if (SkipDGRegs && DowngradedRegs.count(Reg))  in getFreePhysReg()
1449     if (reservedRegs_.test(Reg))  in getFreePhysReg()
1452     if (isRegAvail(Reg) && (!SkipDGRegs || !isRecentlyUsed(Reg))) {  in getFreePhysReg()
1453       FreeReg = Reg;  in getFreePhysReg()
1475     unsigned Reg = Order[i];  in getFreePhysReg()  local
1477     if (SkipDGRegs && DowngradedRegs.count(Reg))  in getFreePhysReg()
1480     if (reservedRegs_.test(Reg))  in getFreePhysReg()
1482     if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&  in getFreePhysReg()
1483         FreeRegInactiveCount < inactiveCounts[Reg] &&  in getFreePhysReg()
1484         (!SkipDGRegs || !isRecentlyUsed(Reg))) {  in getFreePhysReg()
1485       FreeReg = Reg;  in getFreePhysReg()
1486       FreeRegInactiveCount = inactiveCounts[Reg];  in getFreePhysReg()