• Home
  • Raw
  • Download

Lines Matching refs:TRI

63     const TargetRegisterInfo *TRI;  member in __anon3ca1cbf20111::TwoAddressInstructionPass
266 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); in Sink3AddrInstruction()
508 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible() argument
513 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
558 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) && in isProfitableToCommute()
560 regsAreCompatible(FromRegB, ToRegC, TRI) || in isProfitableToCommute()
561 regsAreCompatible(FromRegC, ToRegB, TRI))) in isProfitableToCommute()
634 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); in isProfitableToConv3Addr()
651 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) in ConvertInstTo3Addr()
947 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI); in TryInstructionTransform()
959 NewMIs[1]->addRegisterKilled(Reg, TRI); in TryInstructionTransform()
1034 TRI = TM.getRegisterInfo(); in runOnMachineFunction()
1174 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); in runOnMachineFunction()
1235 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI); in runOnMachineFunction()
1281 const TargetRegisterInfo &TRI) { in UpdateRegSequenceSrcs() argument
1286 MO.substVirtReg(DstReg, SubIdx, TRI); in UpdateRegSequenceSrcs()
1336 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, in CoalesceExtSubRegs()
1343 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, in CoalesceExtSubRegs()
1366 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || in CoalesceExtSubRegs()
1368 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { in CoalesceExtSubRegs()
1465 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), in EliminateRegSequences()
1508 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); in EliminateRegSequences()