616                                    unsigned DestReg, unsigned SrcReg,  in copyPhysReg()  argument
618   bool GPRDest = ARM::GPRRegClass.contains(DestReg);  in copyPhysReg()
622     AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)  in copyPhysReg()
627   bool SPRDest = ARM::SPRRegClass.contains(DestReg);  in copyPhysReg()
637   else if (ARM::DPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
639   else if (ARM::QPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
641   else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
643   else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
648   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);  in copyPhysReg()
814                      unsigned DestReg, int FI,  in loadRegFromStackSlot()  argument
837     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)  in loadRegFromStackSlot()
841     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)  in loadRegFromStackSlot()
847     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)  in loadRegFromStackSlot()
854       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)  in loadRegFromStackSlot()
858       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)  in loadRegFromStackSlot()
866       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)  in loadRegFromStackSlot()
874       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);  in loadRegFromStackSlot()
875       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);  in loadRegFromStackSlot()
876       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);  in loadRegFromStackSlot()
877             AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);  in loadRegFromStackSlot()
885     MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);  in loadRegFromStackSlot()
886     MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);  in loadRegFromStackSlot()
887     MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);  in loadRegFromStackSlot()
888     MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);  in loadRegFromStackSlot()
889     MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);  in loadRegFromStackSlot()
890     MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);  in loadRegFromStackSlot()
891     MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);  in loadRegFromStackSlot()
892     AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);  in loadRegFromStackSlot()
997               unsigned DestReg, unsigned SubIdx,  in reMaterialize()  argument
1004     MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);  in reMaterialize()
1014                                       DestReg)  in reMaterialize()
1335                                unsigned DestReg, unsigned BaseReg, int NumBytes,  in emitARMRegPlusImmediate()  argument
1353     BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitARMRegPlusImmediate()
1357     BaseReg = DestReg;  in emitARMRegPlusImmediate()