Lines Matching refs:getOperand
146 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); in convertToThreeAddress()
147 const MachineOperand &Base = MI->getOperand(2); in convertToThreeAddress()
148 const MachineOperand &Offset = MI->getOperand(NumOps-3); in convertToThreeAddress()
152 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); in convertToThreeAddress()
153 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); in convertToThreeAddress()
206 get(MemOpc), MI->getOperand(0).getReg()) in convertToThreeAddress()
210 get(MemOpc)).addReg(MI->getOperand(1).getReg()) in convertToThreeAddress()
217 get(MemOpc), MI->getOperand(0).getReg()) in convertToThreeAddress()
221 get(MemOpc)).addReg(MI->getOperand(1).getReg()) in convertToThreeAddress()
224 UpdateMI->getOperand(0).setIsDead(); in convertToThreeAddress()
232 MachineOperand &MO = MI->getOperand(i); in convertToThreeAddress()
289 TBB = LastInst->getOperand(0).getMBB(); in AnalyzeBranch()
294 TBB = LastInst->getOperand(0).getMBB(); in AnalyzeBranch()
295 Cond.push_back(LastInst->getOperand(1)); in AnalyzeBranch()
296 Cond.push_back(LastInst->getOperand(2)); in AnalyzeBranch()
315 TBB = LastInst->getOperand(0).getMBB(); in AnalyzeBranch()
330 TBB = SecondLastInst->getOperand(0).getMBB(); in AnalyzeBranch()
331 Cond.push_back(SecondLastInst->getOperand(1)); in AnalyzeBranch()
332 Cond.push_back(SecondLastInst->getOperand(2)); in AnalyzeBranch()
333 FBB = LastInst->getOperand(0).getMBB(); in AnalyzeBranch()
340 TBB = SecondLastInst->getOperand(0).getMBB(); in AnalyzeBranch()
444 MachineOperand &PMO = MI->getOperand(PIdx); in PredicateInstruction()
446 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); in PredicateInstruction()
488 const MachineOperand &MO = MI->getOperand(i); in DefinesPredicate()
537 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); in GetInstSizeInBytes()
559 return MI->getOperand(2).getImm(); in GetInstSizeInBytes()
585 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2)); in GetInstSizeInBytes()
772 if (MI->getOperand(1).isFI() && in isStoreToStackSlot()
773 MI->getOperand(2).isReg() && in isStoreToStackSlot()
774 MI->getOperand(3).isImm() && in isStoreToStackSlot()
775 MI->getOperand(2).getReg() == 0 && in isStoreToStackSlot()
776 MI->getOperand(3).getImm() == 0) { in isStoreToStackSlot()
777 FrameIndex = MI->getOperand(1).getIndex(); in isStoreToStackSlot()
778 return MI->getOperand(0).getReg(); in isStoreToStackSlot()
786 if (MI->getOperand(1).isFI() && in isStoreToStackSlot()
787 MI->getOperand(2).isImm() && in isStoreToStackSlot()
788 MI->getOperand(2).getImm() == 0) { in isStoreToStackSlot()
789 FrameIndex = MI->getOperand(1).getIndex(); in isStoreToStackSlot()
790 return MI->getOperand(0).getReg(); in isStoreToStackSlot()
794 if (MI->getOperand(0).isFI() && in isStoreToStackSlot()
795 MI->getOperand(2).getSubReg() == 0) { in isStoreToStackSlot()
796 FrameIndex = MI->getOperand(0).getIndex(); in isStoreToStackSlot()
797 return MI->getOperand(2).getReg(); in isStoreToStackSlot()
801 if (MI->getOperand(1).isFI() && in isStoreToStackSlot()
802 MI->getOperand(0).getSubReg() == 0) { in isStoreToStackSlot()
803 FrameIndex = MI->getOperand(1).getIndex(); in isStoreToStackSlot()
804 return MI->getOperand(0).getReg(); in isStoreToStackSlot()
907 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot()
908 MI->getOperand(2).isReg() && in isLoadFromStackSlot()
909 MI->getOperand(3).isImm() && in isLoadFromStackSlot()
910 MI->getOperand(2).getReg() == 0 && in isLoadFromStackSlot()
911 MI->getOperand(3).getImm() == 0) { in isLoadFromStackSlot()
912 FrameIndex = MI->getOperand(1).getIndex(); in isLoadFromStackSlot()
913 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
921 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot()
922 MI->getOperand(2).isImm() && in isLoadFromStackSlot()
923 MI->getOperand(2).getImm() == 0) { in isLoadFromStackSlot()
924 FrameIndex = MI->getOperand(1).getIndex(); in isLoadFromStackSlot()
925 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
929 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot()
930 MI->getOperand(0).getSubReg() == 0) { in isLoadFromStackSlot()
931 FrameIndex = MI->getOperand(1).getIndex(); in isLoadFromStackSlot()
932 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
936 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot()
937 MI->getOperand(0).getSubReg() == 0) { in isLoadFromStackSlot()
938 FrameIndex = MI->getOperand(1).getIndex(); in isLoadFromStackSlot()
939 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
1004 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1011 unsigned CPI = Orig->getOperand(1).getIndex(); in reMaterialize()
1028 unsigned CPI = Orig->getOperand(1).getIndex(); in duplicate()
1030 Orig->getOperand(1).setIndex(CPI); in duplicate()
1031 Orig->getOperand(2).setImm(PCLabelId); in duplicate()
1056 const MachineOperand &MO0 = MI0->getOperand(1); in produceSameValue()
1057 const MachineOperand &MO1 = MI1->getOperand(1); in produceSameValue()
1093 unsigned Addr0 = MI0->getOperand(1).getReg(); in produceSameValue()
1094 unsigned Addr1 = MI1->getOperand(1).getReg(); in produceSameValue()
1112 const MachineOperand &MO0 = MI0->getOperand(i); in produceSameValue()
1113 const MachineOperand &MO1 = MI1->getOperand(i); in produceSameValue()
1176 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1177 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1181 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
1185 if (isa<ConstantSDNode>(Load1->getOperand(1)) && in areLoadsFromSameBasePtr()
1186 isa<ConstantSDNode>(Load2->getOperand(1))) { in areLoadsFromSameBasePtr()
1187 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1188 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1315 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1316 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); in getInstrPredicate()
1374 Offset += MI.getOperand(FrameRegIdx+1).getImm(); in rewriteARMFrameIndex()
1378 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); in rewriteARMFrameIndex()
1391 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); in rewriteARMFrameIndex()
1392 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); in rewriteARMFrameIndex()
1408 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); in rewriteARMFrameIndex()
1417 InstrOffs = MI.getOperand(ImmIdx).getImm(); in rewriteARMFrameIndex()
1423 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); in rewriteARMFrameIndex()
1424 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) in rewriteARMFrameIndex()
1431 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); in rewriteARMFrameIndex()
1432 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) in rewriteARMFrameIndex()
1443 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); in rewriteARMFrameIndex()
1444 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) in rewriteARMFrameIndex()
1465 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteARMFrameIndex()
1470 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); in rewriteARMFrameIndex()
1509 SrcReg = MI->getOperand(0).getReg(); in AnalyzeCompare()
1511 CmpValue = MI->getOperand(1).getImm(); in AnalyzeCompare()
1515 SrcReg = MI->getOperand(0).getReg(); in AnalyzeCompare()
1516 CmpMask = MI->getOperand(1).getImm(); in AnalyzeCompare()
1533 if (CmpMask != MI->getOperand(2).getImm()) in isSuitableForMask()
1535 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) in isSuitableForMask()
1545 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), in isSuitableForMask()
1603 const MachineOperand &MO = Instr.getOperand(IO); in OptimizeCompareInstr()
1664 const MachineOperand &MO = Instr.getOperand(IO); in OptimizeCompareInstr()
1672 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); in OptimizeCompareInstr()
1692 MI->getOperand(5).setReg(ARM::CPSR); in OptimizeCompareInstr()
1693 MI->getOperand(5).setIsDef(true); in OptimizeCompareInstr()
1709 if (!DefMI->getOperand(1).isImm()) in FoldImmediate()
1718 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); in FoldImmediate()
1731 Commute = UseMI->getOperand(2).getReg() != Reg; in FoldImmediate()
1783 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate()
1784 bool isKill = UseMI->getOperand(OpIdx).isKill(); in FoldImmediate()
1792 UseMI->getOperand(1).setReg(NewReg); in FoldImmediate()
1793 UseMI->getOperand(1).setIsKill(); in FoldImmediate()
1794 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); in FoldImmediate()
2177 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); in getOperandLatency()
2204 unsigned ShOpVal = DefMI->getOperand(3).getImm(); in getOperandLatency()
2216 unsigned ShAmt = DefMI->getOperand(3).getImm(); in getOperandLatency()
2364 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); in getOperandLatency()
2377 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); in getOperandLatency()