Lines Matching refs:OpIdx
103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue()
157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
247 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStmModeOpValue()
249 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStSORegOpValue()
289 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OpValue()
291 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OffsetOpValue()
293 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode3OffsetOpValue()
1004 unsigned OpIdx) { in getMachineSoRegOpValue() argument
1007 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); in getMachineSoRegOpValue()
1008 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); in getMachineSoRegOpValue()
1102 unsigned OpIdx = 0; in emitDataProcessingInstruction() local
1104 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitDataProcessingInstruction()
1111 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), in emitDataProcessingInstruction()
1119 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), in emitDataProcessingInstruction()
1136 Binary |= getMachineOpValue(MI, OpIdx++); in emitDataProcessingInstruction()
1138 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); in emitDataProcessingInstruction()
1139 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; in emitDataProcessingInstruction()
1149 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitDataProcessingInstruction()
1150 ++OpIdx; in emitDataProcessingInstruction()
1159 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; in emitDataProcessingInstruction()
1160 ++OpIdx; in emitDataProcessingInstruction()
1165 const MachineOperand &MO = MI.getOperand(OpIdx); in emitDataProcessingInstruction()
1168 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); in emitDataProcessingInstruction()
1210 unsigned OpIdx = 0; in emitLoadStoreInstruction() local
1216 ++OpIdx; in emitLoadStoreInstruction()
1225 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitLoadStoreInstruction()
1232 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitLoadStoreInstruction()
1235 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitLoadStoreInstruction()
1236 ++OpIdx; in emitLoadStoreInstruction()
1238 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitLoadStoreInstruction()
1240 ? 0 : MI.getOperand(OpIdx+1).getImm(); in emitLoadStoreInstruction()
1281 unsigned OpIdx = 0; in emitMiscLoadStoreInstruction() local
1287 ++OpIdx; in emitMiscLoadStoreInstruction()
1292 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitMiscLoadStoreInstruction()
1296 ++OpIdx; in emitMiscLoadStoreInstruction()
1303 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitMiscLoadStoreInstruction()
1306 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitMiscLoadStoreInstruction()
1307 ++OpIdx; in emitMiscLoadStoreInstruction()
1309 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitMiscLoadStoreInstruction()
1311 ? 0 : MI.getOperand(OpIdx+1).getImm(); in emitMiscLoadStoreInstruction()
1371 unsigned OpIdx = 0; in emitLoadStoreMultipleInstruction() local
1373 ++OpIdx; in emitLoadStoreMultipleInstruction()
1376 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitLoadStoreMultipleInstruction()
1387 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { in emitLoadStoreMultipleInstruction()
1414 unsigned OpIdx = 0; in emitMulFrmInstruction() local
1416 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; in emitMulFrmInstruction()
1419 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; in emitMulFrmInstruction()
1422 Binary |= getMachineOpValue(MI, OpIdx++); in emitMulFrmInstruction()
1425 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; in emitMulFrmInstruction()
1429 if (MCID.getNumOperands() > OpIdx && in emitMulFrmInstruction()
1430 !MCID.OpInfo[OpIdx].isPredicate() && in emitMulFrmInstruction()
1431 !MCID.OpInfo[OpIdx].isOptionalDef()) in emitMulFrmInstruction()
1432 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; in emitMulFrmInstruction()
1446 unsigned OpIdx = 0; in emitExtendInstruction() local
1449 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitExtendInstruction()
1451 const MachineOperand &MO1 = MI.getOperand(OpIdx++); in emitExtendInstruction()
1452 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitExtendInstruction()
1460 ++OpIdx; in emitExtendInstruction()
1466 if (MI.getOperand(OpIdx).isImm() && in emitExtendInstruction()
1467 !MCID.OpInfo[OpIdx].isPredicate() && in emitExtendInstruction()
1468 !MCID.OpInfo[OpIdx].isOptionalDef()) in emitExtendInstruction()
1469 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; in emitExtendInstruction()
1489 unsigned OpIdx = 0; in emitMiscArithInstruction() local
1492 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitMiscArithInstruction()
1494 const MachineOperand &MO = MI.getOperand(OpIdx++); in emitMiscArithInstruction()
1495 if (OpIdx == MCID.getNumOperands() || in emitMiscArithInstruction()
1496 MCID.OpInfo[OpIdx].isPredicate() || in emitMiscArithInstruction()
1497 MCID.OpInfo[OpIdx].isOptionalDef()) { in emitMiscArithInstruction()
1508 Binary |= getMachineOpValue(MI, OpIdx++); in emitMiscArithInstruction()
1511 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); in emitMiscArithInstruction()
1646 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { in encodeVFPRd() argument
1647 unsigned RegD = MI.getOperand(OpIdx).getReg(); in encodeVFPRd()
1661 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { in encodeVFPRn() argument
1662 unsigned RegN = MI.getOperand(OpIdx).getReg(); in encodeVFPRn()
1676 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { in encodeVFPRm() argument
1677 unsigned RegM = MI.getOperand(OpIdx).getReg(); in encodeVFPRm()
1700 unsigned OpIdx = 0; in emitVFPArithInstruction() local
1703 Binary |= encodeVFPRd(MI, OpIdx++); in emitVFPArithInstruction()
1706 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitVFPArithInstruction()
1707 ++OpIdx; in emitVFPArithInstruction()
1711 Binary |= encodeVFPRn(MI, OpIdx++); in emitVFPArithInstruction()
1713 if (OpIdx == MCID.getNumOperands() || in emitVFPArithInstruction()
1714 MCID.OpInfo[OpIdx].isPredicate() || in emitVFPArithInstruction()
1715 MCID.OpInfo[OpIdx].isOptionalDef()) { in emitVFPArithInstruction()
1722 Binary |= encodeVFPRm(MI, OpIdx); in emitVFPArithInstruction()
1796 unsigned OpIdx = 0; in emitVFPLoadStoreInstruction() local
1799 Binary |= encodeVFPRd(MI, OpIdx++); in emitVFPLoadStoreInstruction()
1802 const MachineOperand &Base = MI.getOperand(OpIdx++); in emitVFPLoadStoreInstruction()
1807 const MachineOperand &Offset = MI.getOperand(OpIdx); in emitVFPLoadStoreInstruction()
1835 unsigned OpIdx = 0; in emitVFPLoadStoreMultipleInstruction() local
1837 ++OpIdx; in emitVFPLoadStoreMultipleInstruction()
1840 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitVFPLoadStoreMultipleInstruction()
1851 Binary |= encodeVFPRd(MI, OpIdx+2); in emitVFPLoadStoreMultipleInstruction()
1855 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { in emitVFPLoadStoreMultipleInstruction()
1891 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { in encodeNEONRd() argument
1892 unsigned RegD = MI.getOperand(OpIdx).getReg(); in encodeNEONRd()
1900 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { in encodeNEONRn() argument
1901 unsigned RegN = MI.getOperand(OpIdx).getReg(); in encodeNEONRn()
1909 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { in encodeNEONRm() argument
1910 unsigned RegM = MI.getOperand(OpIdx).getReg(); in encodeNEONRm()
2002 unsigned OpIdx = 0; in emitNEON2RegInstruction() local
2003 Binary |= encodeNEONRd(MI, OpIdx++); in emitNEON2RegInstruction()
2004 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON2RegInstruction()
2005 ++OpIdx; in emitNEON2RegInstruction()
2006 Binary |= encodeNEONRm(MI, OpIdx); in emitNEON2RegInstruction()
2017 unsigned OpIdx = 0; in emitNEON3RegInstruction() local
2018 Binary |= encodeNEONRd(MI, OpIdx++); in emitNEON3RegInstruction()
2019 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON3RegInstruction()
2020 ++OpIdx; in emitNEON3RegInstruction()
2021 Binary |= encodeNEONRn(MI, OpIdx++); in emitNEON3RegInstruction()
2022 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON3RegInstruction()
2023 ++OpIdx; in emitNEON3RegInstruction()
2024 Binary |= encodeNEONRm(MI, OpIdx); in emitNEON3RegInstruction()