Lines Matching refs:Ops
1296 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), in SelectARMIndexedLoad() local
1299 MVT::Other, Ops, 6); in SelectARMIndexedLoad()
1344 SDValue Ops[]= { Base, Offset, getAL(CurDAG), in SelectT2IndexedLoad() local
1347 MVT::Other, Ops, 5); in SelectT2IndexedLoad()
1361 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairSRegs() local
1362 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); in PairSRegs()
1372 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairDRegs() local
1373 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); in PairDRegs()
1383 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairQRegs() local
1384 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); in PairQRegs()
1398 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadSRegs() local
1400 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); in QuadSRegs()
1413 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadDRegs() local
1415 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); in QuadDRegs()
1428 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadQRegs() local
1430 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); in QuadQRegs()
1508 SmallVector<SDValue, 7> Ops; in SelectVLD() local
1514 Ops.push_back(MemAddr); in SelectVLD()
1515 Ops.push_back(Align); in SelectVLD()
1518 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLD()
1520 Ops.push_back(Pred); in SelectVLD()
1521 Ops.push_back(Reg0); in SelectVLD()
1522 Ops.push_back(Chain); in SelectVLD()
1523 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size()); in SelectVLD()
1540 Ops.push_back(SDValue(VLdA, 1)); in SelectVLD()
1541 Ops.push_back(Align); in SelectVLD()
1547 Ops.push_back(Reg0); in SelectVLD()
1549 Ops.push_back(SDValue(VLdA, 0)); in SelectVLD()
1550 Ops.push_back(Pred); in SelectVLD()
1551 Ops.push_back(Reg0); in SelectVLD()
1552 Ops.push_back(Chain); in SelectVLD()
1554 Ops.data(), Ops.size()); in SelectVLD()
1625 SmallVector<SDValue, 7> Ops; in SelectVST() local
1656 Ops.push_back(MemAddr); in SelectVST()
1657 Ops.push_back(Align); in SelectVST()
1660 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVST()
1662 Ops.push_back(SrcReg); in SelectVST()
1663 Ops.push_back(Pred); in SelectVST()
1664 Ops.push_back(Reg0); in SelectVST()
1665 Ops.push_back(Chain); in SelectVST()
1667 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size()); in SelectVST()
1697 Ops.push_back(SDValue(VStA, 0)); in SelectVST()
1698 Ops.push_back(Align); in SelectVST()
1704 Ops.push_back(Reg0); in SelectVST()
1706 Ops.push_back(RegSeq); in SelectVST()
1707 Ops.push_back(Pred); in SelectVST()
1708 Ops.push_back(Reg0); in SelectVST()
1709 Ops.push_back(Chain); in SelectVST()
1711 Ops.data(), Ops.size()); in SelectVST()
1782 SmallVector<SDValue, 8> Ops; in SelectVLDSTLane() local
1783 Ops.push_back(MemAddr); in SelectVLDSTLane()
1784 Ops.push_back(Align); in SelectVLDSTLane()
1787 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLDSTLane()
1808 Ops.push_back(SuperReg); in SelectVLDSTLane()
1809 Ops.push_back(getI32Imm(Lane)); in SelectVLDSTLane()
1810 Ops.push_back(Pred); in SelectVLDSTLane()
1811 Ops.push_back(Reg0); in SelectVLDSTLane()
1812 Ops.push_back(Chain); in SelectVLDSTLane()
1817 Ops.data(), Ops.size()); in SelectVLDSTLane()
1879 SmallVector<SDValue, 6> Ops; in SelectVLDDup() local
1880 Ops.push_back(MemAddr); in SelectVLDDup()
1881 Ops.push_back(Align); in SelectVLDDup()
1884 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLDDup()
1886 Ops.push_back(Pred); in SelectVLDDup()
1887 Ops.push_back(Reg0); in SelectVLDDup()
1888 Ops.push_back(Chain); in SelectVLDDup()
1897 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size()); in SelectVLDDup()
1936 SmallVector<SDValue, 6> Ops; in SelectVTBL() local
1938 Ops.push_back(N->getOperand(1)); in SelectVTBL()
1939 Ops.push_back(RegSeq); in SelectVTBL()
1940 Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); in SelectVTBL()
1941 Ops.push_back(getAL(CurDAG)); // predicate in SelectVTBL()
1942 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register in SelectVTBL()
1943 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size()); in SelectVTBL()
1972 SDValue Ops[] = { N->getOperand(0).getOperand(0), in SelectV6T2BitfieldExtractOp() local
1976 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); in SelectV6T2BitfieldExtractOp()
1994 SDValue Ops[] = { N->getOperand(0).getOperand(0), in SelectV6T2BitfieldExtractOp() local
1998 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); in SelectV6T2BitfieldExtractOp()
2025 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; in SelectT2CMOVShiftOp() local
2026 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6); in SelectT2CMOVShiftOp()
2039 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; in SelectARMCMOVShiftOp() local
2040 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7); in SelectARMCMOVShiftOp()
2069 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; in SelectT2CMOVImmOp() local
2070 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); in SelectT2CMOVImmOp()
2102 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; in SelectARMCMOVImmOp() local
2103 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); in SelectARMCMOVImmOp()
2181 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag }; in SelectCMOVOp() local
2198 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); in SelectCMOVOp()
2246 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select() local
2248 Ops, 4); in Select()
2250 SDValue Ops[] = { in Select() local
2258 Ops, 5); in Select()
2277 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), in Select() local
2280 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); in Select()
2306 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2307 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6); in Select()
2309 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2310 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); in Select()
2322 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2323 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6); in Select()
2325 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2326 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7); in Select()
2365 SDValue Ops[] = { N0.getOperand(0), Imm16, in Select() local
2367 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4); in Select()
2380 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2383 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4); in Select()
2385 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2390 dl, MVT::i32, MVT::i32, Ops, 5); in Select()
2397 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2399 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4); in Select()
2401 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2406 dl, MVT::i32, MVT::i32, Ops, 5); in Select()
2447 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; in Select() local
2449 MVT::Glue, Ops, 5); in Select()
2477 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
2478 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); in Select()
2496 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
2497 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); in Select()
2515 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
2516 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); in Select()
2721 SmallVector<SDValue, 7> Ops; in Select() local
2722 Ops.push_back(MemAddr); in Select()
2723 Ops.push_back(getAL(CurDAG)); in Select()
2724 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
2725 Ops.push_back(Chain); in Select()
2726 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
2727 Ops.size()); in Select()
2788 SmallVector<SDValue, 7> Ops; in Select() local
2789 Ops.push_back(Val0); in Select()
2790 Ops.push_back(Val1); in Select()
2791 Ops.push_back(MemAddr); in Select()
2792 Ops.push_back(getAL(CurDAG)); in Select()
2793 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
2794 Ops.push_back(Chain); in Select()
2800 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
2801 Ops.size()); in Select()
2961 SmallVector<SDValue, 6> Ops; in Select() local
2963 Ops.push_back(N->getOperand(0)); in Select()
2964 Ops.push_back(N->getOperand(1)); in Select()
2965 Ops.push_back(getAL(CurDAG)); // Predicate in Select()
2966 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register in Select()
2967 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size()); in Select()
2978 SmallVector<SDValue, 6> Ops; in Select() local
2979 Ops.push_back(RegSeq); in Select()
2980 Ops.push_back(N->getOperand(2)); in Select()
2981 Ops.push_back(getAL(CurDAG)); // Predicate in Select()
2982 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register in Select()
2984 Ops.data(), Ops.size()); in Select()