Lines Matching refs:SDNode
87 SDNode *Select(SDNode *N);
90 bool hasNoVMLxHazardUse(SDNode *N) const;
125 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
129 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
133 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
134 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
161 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
188 SDNode *SelectARMIndexedLoad(SDNode *N);
189 SDNode *SelectT2IndexedLoad(SDNode *N);
195 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
203 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
210 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
217 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
223 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
226 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
229 SDNode *SelectCMOVOp(SDNode *N);
230 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
233 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
236 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
239 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
243 SDNode *SelectConcatVector(SDNode *N);
252 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
253 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
254 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
257 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
258 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
259 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268 static bool isInt32Immediate(SDNode *N, unsigned &Imm) { in isInt32Immediate()
285 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
315 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const { in hasNoVMLxHazardUse()
328 SDNode *Use = *N->use_begin(); in hasNoVMLxHazardUse()
686 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N, in SelectAddrMode2Offset()
776 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N, in SelectAddrMode3Offset()
839 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr, in SelectAddrMode6()
862 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N, in SelectAddrMode6Offset()
1178 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, in SelectT2AddrModeImm8Offset()
1258 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) { in SelectARMIndexedLoad()
1305 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) { in SelectT2IndexedLoad()
1355 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) { in PairSRegs()
1367 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { in PairDRegs()
1378 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) { in PairQRegs()
1389 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1, in QuadSRegs()
1405 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1, in QuadDRegs()
1420 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1, in QuadQRegs()
1455 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1507 SDNode *VLd; in SelectVLD()
1535 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl, in SelectVLD()
1579 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
1666 SDNode *VSt = in SelectVST()
1690 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl, in SelectVST()
1710 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, in SelectVST()
1716 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, in SelectVLDSTLane()
1816 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, in SelectVLDSTLane()
1836 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, in SelectVLDDup()
1896 SDNode *VLdDup = in SelectVLDDup()
1913 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, in SelectVTBL()
1946 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, in SelectV6T2BitfieldExtractOp()
2004 SDNode *ARMDAGToDAGISel::
2005 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, in SelectT2CMOVShiftOp()
2031 SDNode *ARMDAGToDAGISel::
2032 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, in SelectARMCMOVShiftOp()
2045 SDNode *ARMDAGToDAGISel::
2046 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, in SelectT2CMOVImmOp()
2076 SDNode *ARMDAGToDAGISel::
2077 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, in SelectARMCMOVImmOp()
2109 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) { in SelectCMOVOp()
2129 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal, in SelectCMOVOp()
2137 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal, in SelectCMOVOp()
2153 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal, in SelectCMOVOp()
2161 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal, in SelectCMOVOp()
2201 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) { in SelectConcatVector()
2210 SDNode *ARMDAGToDAGISel::Select(SDNode *N) { in Select()
2242 SDNode *ResNode; in Select()
2284 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) in Select()
2288 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true)) in Select()
2333 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) in Select()
2410 SDNode *ResNode = 0; in Select()
2448 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, in Select()
2726 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
2800 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()