Lines Matching refs:DAG
1091 DebugLoc dl, SelectionDAG &DAG, in LowerCallResult() argument
1096 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult()
1097 getTargetMachine(), RVLocs, *DAG.getContext(), Call); in LowerCallResult()
1109 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1114 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1118 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1121 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1122 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1123 DAG.getConstant(0, MVT::i32)); in LowerCallResult()
1126 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1130 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1133 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1134 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1135 DAG.getConstant(1, MVT::i32)); in LowerCallResult()
1138 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1148 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1162 DebugLoc dl, SelectionDAG &DAG, in LowerMemOpCallTo() argument
1166 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); in LowerMemOpCallTo()
1167 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); in LowerMemOpCallTo()
1168 return DAG.getStore(Chain, dl, Arg, PtrOff, in LowerMemOpCallTo()
1173 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, in PassF64ArgInRegs() argument
1181 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1182 DAG.getVTList(MVT::i32, MVT::i32), Arg); in PassF64ArgInRegs()
1190 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); in PassF64ArgInRegs()
1193 dl, DAG, NextVA, in PassF64ArgInRegs()
1208 DebugLoc dl, SelectionDAG &DAG, in LowerCall() argument
1210 MachineFunction &MF = DAG.getMachineFunction(); in LowerCall()
1220 Outs, OutVals, Ins, DAG); in LowerCall()
1231 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCall()
1232 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); in LowerCall()
1247 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); in LowerCall()
1249 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); in LowerCall()
1269 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1272 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1275 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1278 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1285 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1286 DAG.getConstant(0, MVT::i32)); in LowerCall()
1287 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1288 DAG.getConstant(1, MVT::i32)); in LowerCall()
1290 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, in LowerCall()
1295 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, in LowerCall()
1301 dl, DAG, VA, Flags)); in LowerCall()
1304 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
1316 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); in LowerCall()
1319 SDValue Const = DAG.getConstant(4*i, MVT::i32); in LowerCall()
1320 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); in LowerCall()
1321 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, in LowerCall()
1332 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); in LowerCall()
1333 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, in LowerCall()
1335 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); in LowerCall()
1336 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); in LowerCall()
1337 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, in LowerCall()
1339 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, in LowerCall()
1350 dl, DAG, VA, Flags)); in LowerCall()
1355 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in LowerCall()
1365 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, in LowerCall()
1382 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, in LowerCall()
1411 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); in LowerCall()
1412 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1413 Callee = DAG.getLoad(getPointerTy(), dl, in LowerCall()
1414 DAG.getEntryNode(), CPAddr, in LowerCall()
1422 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), in LowerCall()
1425 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); in LowerCall()
1426 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1427 Callee = DAG.getLoad(getPointerTy(), dl, in LowerCall()
1428 DAG.getEntryNode(), CPAddr, in LowerCall()
1447 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); in LowerCall()
1448 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1449 Callee = DAG.getLoad(getPointerTy(), dl, in LowerCall()
1450 DAG.getEntryNode(), CPAddr, in LowerCall()
1453 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerCall()
1454 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, in LowerCall()
1462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); in LowerCall()
1473 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), in LowerCall()
1475 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); in LowerCall()
1476 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1477 Callee = DAG.getLoad(getPointerTy(), dl, in LowerCall()
1478 DAG.getEntryNode(), CPAddr, in LowerCall()
1481 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerCall()
1482 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, in LowerCall()
1490 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); in LowerCall()
1514 Ops.push_back(DAG.getRegister(RegsToPass[i].first, in LowerCall()
1520 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
1522 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); in LowerCall()
1525 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); in LowerCall()
1528 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), in LowerCall()
1529 DAG.getIntPtrConstant(0, true), InFlag); in LowerCall()
1536 dl, DAG, InVals); in LowerCall()
1624 SelectionDAG& DAG) const { in IsEligibleForTailCallOptimization()
1625 const Function *CallerF = DAG.getMachineFunction().getFunction(); in IsEligibleForTailCallOptimization()
1666 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
1667 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); in IsEligibleForTailCallOptimization()
1671 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
1672 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); in IsEligibleForTailCallOptimization()
1698 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
1699 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); in IsEligibleForTailCallOptimization()
1703 MachineFunction &MF = DAG.getMachineFunction(); in IsEligibleForTailCallOptimization()
1752 DebugLoc dl, SelectionDAG &DAG) const { in LowerReturn()
1758 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn()
1759 getTargetMachine(), RVLocs, *DAG.getContext(), Call); in LowerReturn()
1767 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { in LowerReturn()
1770 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
1788 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
1795 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
1796 DAG.getConstant(0, MVT::i32)); in LowerReturn()
1797 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
1798 DAG.getVTList(MVT::i32, MVT::i32), Half); in LowerReturn()
1800 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); in LowerReturn()
1803 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
1809 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
1810 DAG.getConstant(1, MVT::i32)); in LowerReturn()
1814 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
1815 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); in LowerReturn()
1816 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); in LowerReturn()
1819 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), in LowerReturn()
1822 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
1831 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); in LowerReturn()
1833 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); in LowerReturn()
1909 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { in LowerConstantPool() argument
1916 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, in LowerConstantPool()
1919 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, in LowerConstantPool()
1921 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); in LowerConstantPool()
1929 SelectionDAG &DAG) const { in LowerBlockAddress()
1930 MachineFunction &MF = DAG.getMachineFunction(); in LowerBlockAddress()
1939 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); in LowerBlockAddress()
1946 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerBlockAddress()
1948 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); in LowerBlockAddress()
1949 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, in LowerBlockAddress()
1954 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerBlockAddress()
1955 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); in LowerBlockAddress()
1961 SelectionDAG &DAG) const { in LowerToTLSGeneralDynamicModel()
1965 MachineFunction &MF = DAG.getMachineFunction(); in LowerToTLSGeneralDynamicModel()
1971 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerToTLSGeneralDynamicModel()
1972 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); in LowerToTLSGeneralDynamicModel()
1973 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, in LowerToTLSGeneralDynamicModel()
1978 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerToTLSGeneralDynamicModel()
1979 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); in LowerToTLSGeneralDynamicModel()
1985 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); in LowerToTLSGeneralDynamicModel()
1989 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), in LowerToTLSGeneralDynamicModel()
1992 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); in LowerToTLSGeneralDynamicModel()
2000 SelectionDAG &DAG) const { in LowerToTLSExecModels()
2004 SDValue Chain = DAG.getEntryNode(); in LowerToTLSExecModels()
2007 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); in LowerToTLSExecModels()
2010 MachineFunction &MF = DAG.getMachineFunction(); in LowerToTLSExecModels()
2018 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerToTLSExecModels()
2019 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); in LowerToTLSExecModels()
2020 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, in LowerToTLSExecModels()
2025 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerToTLSExecModels()
2026 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); in LowerToTLSExecModels()
2028 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, in LowerToTLSExecModels()
2034 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerToTLSExecModels()
2035 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); in LowerToTLSExecModels()
2036 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, in LowerToTLSExecModels()
2043 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); in LowerToTLSExecModels()
2047 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { in LowerGlobalTLSAddress()
2055 return LowerToTLSGeneralDynamicModel(GA, DAG); in LowerGlobalTLSAddress()
2057 return LowerToTLSExecModels(GA, DAG); in LowerGlobalTLSAddress()
2061 SelectionDAG &DAG) const { in LowerGlobalAddressELF()
2070 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerGlobalAddressELF()
2071 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressELF()
2072 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), in LowerGlobalAddressELF()
2077 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); in LowerGlobalAddressELF()
2078 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); in LowerGlobalAddressELF()
2080 Result = DAG.getLoad(PtrVT, dl, Chain, Result, in LowerGlobalAddressELF()
2091 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, in LowerGlobalAddressELF()
2092 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); in LowerGlobalAddressELF()
2094 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); in LowerGlobalAddressELF()
2095 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressELF()
2096 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerGlobalAddressELF()
2103 SelectionDAG &DAG) const { in LowerGlobalAddressDarwin()
2108 MachineFunction &MF = DAG.getMachineFunction(); in LowerGlobalAddressDarwin()
2117 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, in LowerGlobalAddressDarwin()
2118 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); in LowerGlobalAddressDarwin()
2122 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, in LowerGlobalAddressDarwin()
2123 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); in LowerGlobalAddressDarwin()
2125 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, in LowerGlobalAddressDarwin()
2133 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); in LowerGlobalAddressDarwin()
2139 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerGlobalAddressDarwin()
2141 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressDarwin()
2143 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerGlobalAddressDarwin()
2149 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerGlobalAddressDarwin()
2150 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); in LowerGlobalAddressDarwin()
2154 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), in LowerGlobalAddressDarwin()
2161 SelectionDAG &DAG) const { in LowerGLOBAL_OFFSET_TABLE()
2164 MachineFunction &MF = DAG.getMachineFunction(); in LowerGLOBAL_OFFSET_TABLE()
2170 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), in LowerGLOBAL_OFFSET_TABLE()
2173 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerGLOBAL_OFFSET_TABLE()
2174 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGLOBAL_OFFSET_TABLE()
2175 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerGLOBAL_OFFSET_TABLE()
2178 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerGLOBAL_OFFSET_TABLE()
2179 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); in LowerGLOBAL_OFFSET_TABLE()
2183 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) in LowerEH_SJLJ_DISPATCHSETUP()
2186 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, in LowerEH_SJLJ_DISPATCHSETUP()
2191 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { in LowerEH_SJLJ_SETJMP()
2193 SDValue Val = DAG.getConstant(0, MVT::i32); in LowerEH_SJLJ_SETJMP()
2194 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0), in LowerEH_SJLJ_SETJMP()
2199 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { in LowerEH_SJLJ_LONGJMP()
2201 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), in LowerEH_SJLJ_LONGJMP()
2202 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); in LowerEH_SJLJ_LONGJMP()
2206 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, in LowerINTRINSIC_WO_CHAIN() argument
2213 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); in LowerINTRINSIC_WO_CHAIN()
2214 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); in LowerINTRINSIC_WO_CHAIN()
2217 MachineFunction &MF = DAG.getMachineFunction(); in LowerINTRINSIC_WO_CHAIN()
2229 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerINTRINSIC_WO_CHAIN()
2230 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerINTRINSIC_WO_CHAIN()
2232 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerINTRINSIC_WO_CHAIN()
2237 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
2238 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); in LowerINTRINSIC_WO_CHAIN()
2246 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2252 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, in LowerMEMBARRIER() argument
2261 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), in LowerMEMBARRIER()
2262 DAG.getConstant(0, MVT::i32)); in LowerMEMBARRIER()
2276 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), in LowerMEMBARRIER()
2277 DAG.getConstant(DMBOpt, MVT::i32)); in LowerMEMBARRIER()
2280 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, in LowerPREFETCH() argument
2302 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), in LowerPREFETCH()
2303 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), in LowerPREFETCH()
2304 DAG.getConstant(isData, MVT::i32)); in LowerPREFETCH()
2307 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { in LowerVASTART() argument
2308 MachineFunction &MF = DAG.getMachineFunction(); in LowerVASTART()
2314 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); in LowerVASTART()
2315 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); in LowerVASTART()
2317 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), in LowerVASTART()
2323 SDValue &Root, SelectionDAG &DAG, in GetF64FormalArgument() argument
2325 MachineFunction &MF = DAG.getMachineFunction(); in GetF64FormalArgument()
2336 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument()
2344 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); in GetF64FormalArgument()
2345 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, in GetF64FormalArgument()
2350 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument()
2353 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
2384 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, in VarArgStyleRegisters() argument
2387 MachineFunction &MF = DAG.getMachineFunction(); in VarArgStyleRegisters()
2409 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), in VarArgStyleRegisters()
2421 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in VarArgStyleRegisters()
2423 DAG.getStore(Val.getValue(1), dl, Val, FIN, in VarArgStyleRegisters()
2427 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, in VarArgStyleRegisters()
2428 DAG.getConstant(4, getPointerTy())); in VarArgStyleRegisters()
2431 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in VarArgStyleRegisters()
2443 DebugLoc dl, SelectionDAG &DAG, in LowerFormalArguments() argument
2446 MachineFunction &MF = DAG.getMachineFunction(); in LowerFormalArguments()
2453 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments()
2454 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); in LowerFormalArguments()
2475 Chain, DAG, dl); in LowerFormalArguments()
2480 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); in LowerFormalArguments()
2481 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, in LowerFormalArguments()
2486 Chain, DAG, dl); in LowerFormalArguments()
2488 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerFormalArguments()
2489 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
2490 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); in LowerFormalArguments()
2491 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
2492 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); in LowerFormalArguments()
2494 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()
2513 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
2523 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
2526 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
2527 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
2528 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
2531 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
2532 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
2533 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
2560 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); in LowerFormalArguments()
2565 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); in LowerFormalArguments()
2571 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); in LowerFormalArguments()
2572 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, in LowerFormalArguments()
2583 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); in LowerFormalArguments()
2608 SDValue &ARMcc, SelectionDAG &DAG, in getARMCmp() argument
2620 RHS = DAG.getConstant(C-1, MVT::i32); in getARMCmp()
2627 RHS = DAG.getConstant(C-1, MVT::i32); in getARMCmp()
2634 RHS = DAG.getConstant(C+1, MVT::i32); in getARMCmp()
2641 RHS = DAG.getConstant(C+1, MVT::i32); in getARMCmp()
2660 ARMcc = DAG.getConstant(CondCode, MVT::i32); in getARMCmp()
2661 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); in getARMCmp()
2666 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, in getVFPCmp() argument
2670 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); in getVFPCmp()
2672 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); in getVFPCmp()
2673 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); in getVFPCmp()
2679 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { in duplicateCmp()
2683 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); in duplicateCmp()
2689 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); in duplicateCmp()
2692 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); in duplicateCmp()
2694 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); in duplicateCmp()
2697 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT()
2732 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); in LowerSELECT()
2734 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); in LowerSELECT()
2739 return DAG.getSelectCC(dl, Cond, in LowerSELECT()
2740 DAG.getConstant(0, Cond.getValueType()), in LowerSELECT()
2744 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC()
2755 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
2756 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); in LowerSELECT_CC()
2757 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp); in LowerSELECT_CC()
2763 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); in LowerSELECT_CC()
2764 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); in LowerSELECT_CC()
2765 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
2766 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, in LowerSELECT_CC()
2769 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); in LowerSELECT_CC()
2771 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); in LowerSELECT_CC()
2772 Result = DAG.getNode(ARMISD::CMOV, dl, VT, in LowerSELECT_CC()
2801 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { in bitcastf32Toi32() argument
2803 return DAG.getConstant(0, MVT::i32); in bitcastf32Toi32()
2806 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), in bitcastf32Toi32()
2814 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, in expandf64Toi32() argument
2817 RetVal1 = DAG.getConstant(0, MVT::i32); in expandf64Toi32()
2818 RetVal2 = DAG.getConstant(0, MVT::i32); in expandf64Toi32()
2824 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), in expandf64Toi32()
2832 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), in expandf64Toi32()
2833 PtrType, Ptr, DAG.getConstant(4, PtrType)); in expandf64Toi32()
2834 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), in expandf64Toi32()
2848 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { in OptimizeVFPBrcond()
2861 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { in OptimizeVFPBrcond()
2872 LHS = bitcastf32Toi32(LHS, DAG); in OptimizeVFPBrcond()
2873 RHS = bitcastf32Toi32(RHS, DAG); in OptimizeVFPBrcond()
2874 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); in OptimizeVFPBrcond()
2875 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
2876 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in OptimizeVFPBrcond()
2882 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
2883 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
2885 ARMcc = DAG.getConstant(CondCode, MVT::i32); in OptimizeVFPBrcond()
2886 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in OptimizeVFPBrcond()
2888 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); in OptimizeVFPBrcond()
2894 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { in LowerBR_CC()
2904 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); in LowerBR_CC()
2905 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
2906 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in LowerBR_CC()
2915 SDValue Result = OptimizeVFPBrcond(Op, DAG); in LowerBR_CC()
2923 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); in LowerBR_CC()
2924 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); in LowerBR_CC()
2925 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
2926 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in LowerBR_CC()
2928 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); in LowerBR_CC()
2930 ARMcc = DAG.getConstant(CondCode2, MVT::i32); in LowerBR_CC()
2932 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); in LowerBR_CC()
2937 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { in LowerBR_JT()
2945 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); in LowerBR_JT()
2946 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); in LowerBR_JT()
2947 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); in LowerBR_JT()
2948 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); in LowerBR_JT()
2949 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); in LowerBR_JT()
2950 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); in LowerBR_JT()
2956 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, in LowerBR_JT()
2960 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, in LowerBR_JT()
2964 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); in LowerBR_JT()
2965 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); in LowerBR_JT()
2967 Addr = DAG.getLoad(PTy, dl, Chain, Addr, in LowerBR_JT()
2970 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); in LowerBR_JT()
2974 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { in LowerFP_TO_INT() argument
2988 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); in LowerFP_TO_INT()
2989 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); in LowerFP_TO_INT()
2992 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { in LowerVectorINT_TO_FP() argument
2999 return DAG.UnrollVectorOp(Op.getNode()); in LowerVectorINT_TO_FP()
3016 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); in LowerVectorINT_TO_FP()
3017 return DAG.getNode(Opc, dl, VT, Op); in LowerVectorINT_TO_FP()
3020 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { in LowerINT_TO_FP() argument
3023 return LowerVectorINT_TO_FP(Op, DAG); in LowerINT_TO_FP()
3039 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); in LowerINT_TO_FP()
3040 return DAG.getNode(Opc, dl, VT, Op); in LowerINT_TO_FP()
3043 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { in LowerFCOPYSIGN()
3057 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, in LowerFCOPYSIGN()
3058 DAG.getTargetConstant(EncodedVal, MVT::i32)); in LowerFCOPYSIGN()
3061 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3062 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
3063 DAG.getConstant(32, MVT::i32)); in LowerFCOPYSIGN()
3065 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
3067 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
3069 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3070 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
3071 DAG.getConstant(32, MVT::i32)); in LowerFCOPYSIGN()
3073 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, in LowerFCOPYSIGN()
3074 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
3075 DAG.getConstant(32, MVT::i32)); in LowerFCOPYSIGN()
3076 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
3077 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
3079 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), in LowerFCOPYSIGN()
3081 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
3082 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, in LowerFCOPYSIGN()
3083 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
3085 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, in LowerFCOPYSIGN()
3086 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), in LowerFCOPYSIGN()
3087 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
3089 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); in LowerFCOPYSIGN()
3090 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, in LowerFCOPYSIGN()
3091 DAG.getConstant(0, MVT::i32)); in LowerFCOPYSIGN()
3093 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); in LowerFCOPYSIGN()
3101 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3103 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); in LowerFCOPYSIGN()
3106 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); in LowerFCOPYSIGN()
3107 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); in LowerFCOPYSIGN()
3108 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
3110 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
3111 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
3112 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in LowerFCOPYSIGN()
3113 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
3117 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3120 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); in LowerFCOPYSIGN()
3121 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); in LowerFCOPYSIGN()
3122 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
3125 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ in LowerRETURNADDR()
3126 MachineFunction &MF = DAG.getMachineFunction(); in LowerRETURNADDR()
3134 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); in LowerRETURNADDR()
3135 SDValue Offset = DAG.getConstant(4, MVT::i32); in LowerRETURNADDR()
3136 return DAG.getLoad(VT, dl, DAG.getEntryNode(), in LowerRETURNADDR()
3137 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), in LowerRETURNADDR()
3143 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); in LowerRETURNADDR()
3146 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { in LowerFRAMEADDR()
3147 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); in LowerFRAMEADDR()
3155 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); in LowerFRAMEADDR()
3157 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, in LowerFRAMEADDR()
3168 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { in ExpandBITCAST() argument
3169 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in ExpandBITCAST()
3182 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, in ExpandBITCAST()
3183 DAG.getConstant(0, MVT::i32)); in ExpandBITCAST()
3184 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, in ExpandBITCAST()
3185 DAG.getConstant(1, MVT::i32)); in ExpandBITCAST()
3186 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
3187 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
3192 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
3193 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); in ExpandBITCAST()
3195 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
3207 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { in getZeroVector() argument
3210 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); in getZeroVector()
3212 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); in getZeroVector()
3213 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in getZeroVector()
3219 SelectionDAG &DAG) const { in LowerShiftRightParts()
3232 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerShiftRightParts()
3233 DAG.getConstant(VTBits, MVT::i32), ShAmt); in LowerShiftRightParts()
3234 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts()
3235 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerShiftRightParts()
3236 DAG.getConstant(VTBits, MVT::i32)); in LowerShiftRightParts()
3237 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts()
3238 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
3239 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); in LowerShiftRightParts()
3241 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts()
3242 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, in LowerShiftRightParts()
3243 ARMcc, DAG, dl); in LowerShiftRightParts()
3244 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); in LowerShiftRightParts()
3245 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, in LowerShiftRightParts()
3249 return DAG.getMergeValues(Ops, 2, dl); in LowerShiftRightParts()
3255 SelectionDAG &DAG) const { in LowerShiftLeftParts()
3266 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerShiftLeftParts()
3267 DAG.getConstant(VTBits, MVT::i32), ShAmt); in LowerShiftLeftParts()
3268 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts()
3269 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerShiftLeftParts()
3270 DAG.getConstant(VTBits, MVT::i32)); in LowerShiftLeftParts()
3271 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts()
3272 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts()
3274 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
3275 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftLeftParts()
3276 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, in LowerShiftLeftParts()
3277 ARMcc, DAG, dl); in LowerShiftLeftParts()
3278 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerShiftLeftParts()
3279 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()
3283 return DAG.getMergeValues(Ops, 2, dl); in LowerShiftLeftParts()
3287 SelectionDAG &DAG) const { in LowerFLT_ROUNDS_()
3293 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in LowerFLT_ROUNDS_()
3294 DAG.getConstant(Intrinsic::arm_get_fpscr, in LowerFLT_ROUNDS_()
3296 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
3297 DAG.getConstant(1U << 22, MVT::i32)); in LowerFLT_ROUNDS_()
3298 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, in LowerFLT_ROUNDS_()
3299 DAG.getConstant(22, MVT::i32)); in LowerFLT_ROUNDS_()
3300 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, in LowerFLT_ROUNDS_()
3301 DAG.getConstant(3, MVT::i32)); in LowerFLT_ROUNDS_()
3304 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, in LowerCTTZ() argument
3312 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); in LowerCTTZ()
3313 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); in LowerCTTZ()
3316 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, in LowerShift() argument
3329 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, in LowerShift()
3330 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), in LowerShift()
3340 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, in LowerShift()
3341 getZeroVector(ShiftVT, DAG, dl), in LowerShift()
3346 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, in LowerShift()
3347 DAG.getConstant(vshiftInt, MVT::i32), in LowerShift()
3351 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, in Expand64BitShift() argument
3372 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), in Expand64BitShift()
3373 DAG.getConstant(0, MVT::i32)); in Expand64BitShift()
3374 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), in Expand64BitShift()
3375 DAG.getConstant(1, MVT::i32)); in Expand64BitShift()
3380 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); in Expand64BitShift()
3383 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); in Expand64BitShift()
3386 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
3389 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { in LowerVSETCC() argument
3427 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); in LowerVSETCC()
3428 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); in LowerVSETCC()
3436 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); in LowerVSETCC()
3437 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); in LowerVSETCC()
3471 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); in LowerVSETCC()
3472 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); in LowerVSETCC()
3498 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; in LowerVSETCC()
3500 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; in LowerVSETCC()
3502 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; in LowerVSETCC()
3504 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; in LowerVSETCC()
3506 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; in LowerVSETCC()
3508 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); in LowerVSETCC()
3511 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); in LowerVSETCC()
3515 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
3524 unsigned SplatBitSize, SelectionDAG &DAG, in isNEONModifiedImm() argument
3654 return DAG.getTargetConstant(EncodedVal, MVT::i32); in isNEONModifiedImm()
3866 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, in IsSingleInstrConstant() argument
3875 return DAG.getConstant(Val, MVT::i32); in IsSingleInstrConstant()
3878 return DAG.getConstant(Val, MVT::i32); in IsSingleInstrConstant()
3885 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, in LowerBUILD_VECTOR() argument
3900 DAG, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
3903 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); in LowerBUILD_VECTOR()
3904 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
3912 DAG, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
3915 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); in LowerBUILD_VECTOR()
3916 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
3943 return DAG.getUNDEF(VT); in LowerBUILD_VECTOR()
3946 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
3954 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); in LowerBUILD_VECTOR()
3958 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, in LowerBUILD_VECTOR()
3960 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in LowerBUILD_VECTOR()
3961 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); in LowerBUILD_VECTOR()
3962 Val = LowerBUILD_VECTOR(Val, DAG, ST); in LowerBUILD_VECTOR()
3964 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
3966 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); in LowerBUILD_VECTOR()
3968 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); in LowerBUILD_VECTOR()
3979 SDValue shuffle = ReconstructShuffle(Op, DAG); in LowerBUILD_VECTOR()
3991 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerBUILD_VECTOR()
3994 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); in LowerBUILD_VECTOR()
3995 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); in LowerBUILD_VECTOR()
3996 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
4005 SelectionDAG &DAG) const { in ReconstructShuffle()
4052 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; in ReconstructShuffle()
4082 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4084 DAG.getIntPtrConstant(NumElts)); in ReconstructShuffle()
4088 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4090 DAG.getIntPtrConstant(0)); in ReconstructShuffle()
4094 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4096 DAG.getIntPtrConstant(0)); in ReconstructShuffle()
4097 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4099 DAG.getIntPtrConstant(NumElts)); in ReconstructShuffle()
4100 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, in ReconstructShuffle()
4101 DAG.getConstant(VEXTOffsets[i], MVT::i32)); in ReconstructShuffle()
4126 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], in ReconstructShuffle()
4181 SDValue RHS, SelectionDAG &DAG, in GeneratePerfectShuffle() argument
4212 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); in GeneratePerfectShuffle()
4213 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); in GeneratePerfectShuffle()
4222 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
4225 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
4228 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
4233 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
4234 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); in GeneratePerfectShuffle()
4238 return DAG.getNode(ARMISD::VEXT, dl, VT, in GeneratePerfectShuffle()
4240 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); in GeneratePerfectShuffle()
4243 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
4247 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
4251 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
4258 SelectionDAG &DAG) { in LowerVECTOR_SHUFFLEv8i8() argument
4267 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); in LowerVECTOR_SHUFFLEv8i8()
4270 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
4271 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, in LowerVECTOR_SHUFFLEv8i8()
4274 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, in LowerVECTOR_SHUFFLEv8i8()
4275 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, in LowerVECTOR_SHUFFLEv8i8()
4279 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { in LowerVECTOR_SHUFFLE() argument
4303 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); in LowerVECTOR_SHUFFLE()
4305 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
4306 DAG.getConstant(Lane, MVT::i32)); in LowerVECTOR_SHUFFLE()
4314 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, in LowerVECTOR_SHUFFLE()
4315 DAG.getConstant(Imm, MVT::i32)); in LowerVECTOR_SHUFFLE()
4319 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
4321 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
4323 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
4332 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4335 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4338 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4342 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4345 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4348 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4371 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); in LowerVECTOR_SHUFFLE()
4379 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerVECTOR_SHUFFLE()
4380 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
4381 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
4385 Ops.push_back(DAG.getUNDEF(EltVT)); in LowerVECTOR_SHUFFLE()
4387 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, in LowerVECTOR_SHUFFLE()
4389 DAG.getConstant(ShuffleMask[i] & (NumElts-1), in LowerVECTOR_SHUFFLE()
4392 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); in LowerVECTOR_SHUFFLE()
4393 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerVECTOR_SHUFFLE()
4397 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); in LowerVECTOR_SHUFFLE()
4405 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { in LowerEXTRACT_VECTOR_ELT() argument
4415 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); in LowerEXTRACT_VECTOR_ELT()
4421 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { in LowerCONCAT_VECTORS() argument
4427 SDValue Val = DAG.getUNDEF(MVT::v2f64); in LowerCONCAT_VECTORS()
4431 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
4432 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), in LowerCONCAT_VECTORS()
4433 DAG.getIntPtrConstant(0)); in LowerCONCAT_VECTORS()
4435 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
4436 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), in LowerCONCAT_VECTORS()
4437 DAG.getIntPtrConstant(1)); in LowerCONCAT_VECTORS()
4438 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); in LowerCONCAT_VECTORS()
4444 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, in isExtendedBUILD_VECTOR() argument
4453 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; in isExtendedBUILD_VECTOR()
4498 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() argument
4501 if (isExtendedBUILD_VECTOR(N, DAG, true)) in isSignExtended()
4508 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() argument
4511 if (isExtendedBUILD_VECTOR(N, DAG, false)) in isZeroExtended()
4518 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { in SkipExtension() argument
4522 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), in SkipExtension()
4531 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; in SkipExtension()
4532 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, in SkipExtension()
4545 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); in SkipExtension()
4547 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), in SkipExtension()
4551 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { in isAddSubSExt() argument
4557 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
4562 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { in isAddSubZExt() argument
4568 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
4573 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { in LowerMUL() argument
4582 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
4583 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
4587 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
4588 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
4594 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
4597 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { in LowerMUL()
4600 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { in LowerMUL()
4620 SDValue Op1 = SkipExtension(N1, DAG); in LowerMUL()
4622 Op0 = SkipExtension(N0, DAG); in LowerMUL()
4626 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
4637 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); in LowerMUL()
4638 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); in LowerMUL()
4640 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
4641 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
4642 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
4643 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
4644 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
4648 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i8() argument
4652 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
4653 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); in LowerSDIV_v4i8()
4654 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
4655 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
4658 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i8()
4659 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); in LowerSDIV_v4i8()
4664 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); in LowerSDIV_v4i8()
4665 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
4666 Y = DAG.getConstant(0xb000, MVT::i32); in LowerSDIV_v4i8()
4667 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); in LowerSDIV_v4i8()
4668 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); in LowerSDIV_v4i8()
4669 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
4671 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
4672 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); in LowerSDIV_v4i8()
4677 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i16() argument
4682 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
4683 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); in LowerSDIV_v4i16()
4684 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
4685 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerSDIV_v4i16()
4690 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
4691 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); in LowerSDIV_v4i16()
4692 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
4693 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), in LowerSDIV_v4i16()
4695 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerSDIV_v4i16()
4700 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
4701 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
4702 N1 = DAG.getConstant(0x89, MVT::i32); in LowerSDIV_v4i16()
4703 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); in LowerSDIV_v4i16()
4704 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
4705 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
4708 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
4709 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
4713 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { in LowerSDIV() argument
4724 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
4725 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); in LowerSDIV()
4727 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
4728 DAG.getIntPtrConstant(4)); in LowerSDIV()
4729 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
4730 DAG.getIntPtrConstant(4)); in LowerSDIV()
4731 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
4732 DAG.getIntPtrConstant(0)); in LowerSDIV()
4733 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
4734 DAG.getIntPtrConstant(0)); in LowerSDIV()
4736 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
4737 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 in LowerSDIV()
4739 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
4740 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerSDIV()
4742 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
4745 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
4748 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { in LowerUDIV() argument
4759 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
4760 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); in LowerUDIV()
4762 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
4763 DAG.getIntPtrConstant(4)); in LowerUDIV()
4764 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
4765 DAG.getIntPtrConstant(4)); in LowerUDIV()
4766 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
4767 DAG.getIntPtrConstant(0)); in LowerUDIV()
4768 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
4769 DAG.getIntPtrConstant(0)); in LowerUDIV()
4771 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
4772 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 in LowerUDIV()
4774 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
4775 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerUDIV()
4777 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
4778 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), in LowerUDIV()
4786 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
4787 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); in LowerUDIV()
4788 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
4789 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerUDIV()
4795 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
4796 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); in LowerUDIV()
4797 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
4798 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), in LowerUDIV()
4800 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
4801 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
4802 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), in LowerUDIV()
4804 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
4809 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
4810 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
4811 N1 = DAG.getConstant(2, MVT::i32); in LowerUDIV()
4812 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); in LowerUDIV()
4813 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
4814 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
4817 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
4818 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
4822 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
4825 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
4826 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
4828 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : in LowerOperation()
4829 LowerGlobalAddressELF(Op, DAG); in LowerOperation()
4830 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
4831 case ISD::SELECT: return LowerSELECT(Op, DAG); in LowerOperation()
4832 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
4833 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
4834 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
4835 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
4836 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); in LowerOperation()
4837 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); in LowerOperation()
4839 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); in LowerOperation()
4841 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); in LowerOperation()
4842 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); in LowerOperation()
4843 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); in LowerOperation()
4844 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); in LowerOperation()
4845 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); in LowerOperation()
4846 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); in LowerOperation()
4847 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); in LowerOperation()
4848 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); in LowerOperation()
4849 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, in LowerOperation()
4851 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); in LowerOperation()
4854 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); in LowerOperation()
4855 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); in LowerOperation()
4857 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); in LowerOperation()
4858 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); in LowerOperation()
4859 case ISD::VSETCC: return LowerVSETCC(Op, DAG); in LowerOperation()
4860 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); in LowerOperation()
4861 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
4862 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
4863 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
4864 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); in LowerOperation()
4865 case ISD::MUL: return LowerMUL(Op, DAG); in LowerOperation()
4866 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
4867 case ISD::UDIV: return LowerUDIV(Op, DAG); in LowerOperation()
4876 SelectionDAG &DAG) const { in ReplaceNodeResults()
4883 Res = ExpandBITCAST(N, DAG); in ReplaceNodeResults()
4887 Res = Expand64BitShift(N, DAG, Subtarget); in ReplaceNodeResults()
5480 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse() local
5481 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in combineSelectAndUse()
5523 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); in combineSelectAndUse()
5525 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, in combineSelectAndUse()
5529 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), in combineSelectAndUse()
5531 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, in combineSelectAndUse()
5599 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL() local
5600 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in AddCombineToVPADDL()
5604 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, in AddCombineToVPADDL()
5621 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), in AddCombineToVPADDL()
5623 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); in AddCombineToVPADDL()
5694 SelectionDAG &DAG = DCI.DAG; in PerformVMULCombine() local
5711 return DAG.getNode(Opcode, DL, VT, in PerformVMULCombine()
5712 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
5713 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
5719 SelectionDAG &DAG = DCI.DAG; in PerformMULCombine() local
5747 Res = DAG.getNode(ISD::ADD, DL, VT, in PerformMULCombine()
5748 V, DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
5749 V, DAG.getConstant(Log2_32(MulAmt-1), in PerformMULCombine()
5753 Res = DAG.getNode(ISD::SUB, DL, VT, in PerformMULCombine()
5754 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
5755 V, DAG.getConstant(Log2_32(MulAmt+1), in PerformMULCombine()
5762 Res = DAG.getNode(ISD::SHL, DL, VT, Res, in PerformMULCombine()
5763 DAG.getConstant(ShiftAmt, MVT::i32)); in PerformMULCombine()
5777 SelectionDAG &DAG = DCI.DAG; in PerformANDCombine() local
5779 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformANDCombine()
5791 DAG, VbicVT, VT.is128BitVector(), in PerformANDCombine()
5795 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); in PerformANDCombine()
5796 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); in PerformANDCombine()
5797 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); in PerformANDCombine()
5813 SelectionDAG &DAG = DCI.DAG; in PerformORCombine() local
5815 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformORCombine()
5827 DAG, VorrVT, VT.is128BitVector(), in PerformORCombine()
5831 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); in PerformORCombine()
5832 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); in PerformORCombine()
5833 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); in PerformORCombine()
5845 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { in PerformORCombine()
5861 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
5864 return DAG.getNode(ISD::BITCAST, dl, VT, Result); in PerformORCombine()
5913 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, in PerformORCombine()
5914 DAG.getConstant(Val, MVT::i32), in PerformORCombine()
5915 DAG.getConstant(Mask, MVT::i32)); in PerformORCombine()
5939 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), in PerformORCombine()
5940 DAG.getConstant(amt, MVT::i32)); in PerformORCombine()
5941 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, in PerformORCombine()
5942 DAG.getConstant(Mask, MVT::i32)); in PerformORCombine()
5955 Res = DAG.getNode(ISD::SRL, DL, VT, N00, in PerformORCombine()
5956 DAG.getConstant(lsb, MVT::i32)); in PerformORCombine()
5957 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, in PerformORCombine()
5958 DAG.getConstant(Mask2, MVT::i32)); in PerformORCombine()
5965 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && in PerformORCombine()
5976 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), in PerformORCombine()
5977 DAG.getConstant(~Mask, MVT::i32)); in PerformORCombine()
6001 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), in PerformBFICombine()
6026 SelectionDAG &DAG = DCI.DAG; in PerformVMOVRRDCombine() local
6029 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, in PerformVMOVRRDCombine()
6033 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformVMOVRRDCombine()
6034 DAG.getConstant(4, MVT::i32)); in PerformVMOVRRDCombine()
6035 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, in PerformVMOVRRDCombine()
6040 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); in PerformVMOVRRDCombine()
6043 DAG.DeleteNode(LD); in PerformVMOVRRDCombine()
6052 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { in PerformVMOVDRRCombine() argument
6063 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in PerformVMOVDRRCombine()
6081 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
6084 SDValue NewST1 = DAG.getStore(St->getChain(), DL, in PerformSTORECombine()
6089 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformSTORECombine()
6090 DAG.getConstant(4, MVT::i32)); in PerformSTORECombine()
6091 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), in PerformSTORECombine()
6101 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
6104 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformSTORECombine()
6106 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); in PerformSTORECombine()
6107 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformSTORECombine()
6110 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); in PerformSTORECombine()
6115 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), in PerformSTORECombine()
6143 SelectionDAG &DAG = DCI.DAG; in PerformBUILD_VECTORCombine() local
6145 SDValue RV = PerformVMOVDRRCombine(N, DAG); in PerformBUILD_VECTORCombine()
6159 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); in PerformBUILD_VECTORCombine()
6164 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); in PerformBUILD_VECTORCombine()
6165 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); in PerformBUILD_VECTORCombine()
6166 return DAG.getNode(ISD::BITCAST, dl, VT, BV); in PerformBUILD_VECTORCombine()
6181 SelectionDAG &DAG = DCI.DAG; in PerformInsertEltCombine() local
6183 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformInsertEltCombine()
6185 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); in PerformInsertEltCombine()
6186 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); in PerformInsertEltCombine()
6190 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine()
6192 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
6197 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { in PerformVECTOR_SHUFFLECombine() argument
6221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformVECTOR_SHUFFLECombine()
6228 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, in PerformVECTOR_SHUFFLECombine()
6244 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, in PerformVECTOR_SHUFFLECombine()
6245 DAG.getUNDEF(VT), NewMask.data()); in PerformVECTOR_SHUFFLECombine()
6255 SelectionDAG &DAG = DCI.DAG; in CombineBaseUpdate() local
6352 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); in CombineBaseUpdate()
6361 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, in CombineBaseUpdate()
6385 SelectionDAG &DAG = DCI.DAG; in CombineVLDDUP() local
6432 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); in CombineVLDDUP()
6435 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, in CombineVLDDUP()
6490 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); in PerformVDUPLANECombine()
6531 SelectionDAG &DAG = DCI.DAG; in PerformVCVTCombine() local
6549 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), in PerformVCVTCombine()
6551 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, in PerformVCVTCombine()
6552 DAG.getConstant(Log2_64(C), MVT::i32)); in PerformVCVTCombine()
6567 SelectionDAG &DAG = DCI.DAG; in PerformVDIVCombine() local
6585 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), in PerformVDIVCombine()
6587 DAG.getConstant(IntrinsicOpcode, MVT::i32), in PerformVDIVCombine()
6588 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); in PerformVDIVCombine()
6640 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { in PerformIntrinsicCombine() argument
6769 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), in PerformIntrinsicCombine()
6770 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); in PerformIntrinsicCombine()
6786 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), in PerformIntrinsicCombine()
6788 DAG.getConstant(Cnt, MVT::i32)); in PerformIntrinsicCombine()
6805 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, in PerformShiftCombine() argument
6810 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformShiftCombine()
6822 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), in PerformShiftCombine()
6823 DAG.getConstant(Cnt, MVT::i32)); in PerformShiftCombine()
6831 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), in PerformShiftCombine()
6832 DAG.getConstant(Cnt, MVT::i32)); in PerformShiftCombine()
6840 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, in PerformExtendCombine() argument
6853 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformExtendCombine()
6871 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); in PerformExtendCombine()
6880 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, in PerformSELECT_CCCombine() argument
6902 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { in PerformSELECT_CCCombine()
6904 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { in PerformSELECT_CCCombine()
6923 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) in PerformSELECT_CCCombine()
6930 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) in PerformSELECT_CCCombine()
6945 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) in PerformSELECT_CCCombine()
6952 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) in PerformSELECT_CCCombine()
6960 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); in PerformSELECT_CCCombine()
6965 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { in PerformCMOVCombine()
6999 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, in PerformCMOVCombine()
7003 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); in PerformCMOVCombine()
7004 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, in PerformCMOVCombine()
7011 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); in PerformCMOVCombine()
7014 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
7015 DAG.getValueType(MVT::i1)); in PerformCMOVCombine()
7017 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
7018 DAG.getValueType(MVT::i8)); in PerformCMOVCombine()
7020 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
7021 DAG.getValueType(MVT::i16)); in PerformCMOVCombine()
7038 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); in PerformDAGCombine()
7042 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
7047 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); in PerformDAGCombine()
7050 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
7053 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
7054 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
7055 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); in PerformDAGCombine()
7320 SelectionDAG &DAG) { in getARMIndexedAddressParts() argument
7332 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); in getARMIndexedAddressParts()
7346 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); in getARMIndexedAddressParts()
7378 SelectionDAG &DAG) { in getT2IndexedAddressParts() argument
7388 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); in getT2IndexedAddressParts()
7392 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); in getT2IndexedAddressParts()
7407 SelectionDAG &DAG) const { in getPreIndexedAddressParts()
7428 Offset, isInc, DAG); in getPreIndexedAddressParts()
7431 Offset, isInc, DAG); in getPreIndexedAddressParts()
7446 SelectionDAG &DAG) const { in getPostIndexedAddressParts()
7467 isInc, DAG); in getPostIndexedAddressParts()
7470 isInc, DAG); in getPostIndexedAddressParts()
7494 const SelectionDAG &DAG, in computeMaskedBitsForTargetNode() argument
7501 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); in computeMaskedBitsForTargetNode()
7505 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, in computeMaskedBitsForTargetNode()
7658 SelectionDAG &DAG) const { in LowerAsmOperandForConstraint()
7809 Result = DAG.getTargetConstant(CVal, Op.getValueType()); in LowerAsmOperandForConstraint()
7817 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); in LowerAsmOperandForConstraint()