Lines Matching refs:Rn
152 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
154 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
159 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
161 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
192 let Inst{4} = Rn{4};
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
223 let Inst{4} = Rn{4};
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
254 let Inst{4} = Rn{4};
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
260 let Inst{4} = Rn{4};
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
386 let Inst{4} = Rn{4};
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
404 let Inst{4} = Rn{4};
440 (ins addrmode6:$Rn), IIC_VLD4,
441 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
443 let Inst{5-4} = Rn{5-4};
458 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
459 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
460 "$Rn.addr = $wb", []> {
461 let Inst{5-4} = Rn{5-4};
526 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
527 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
530 (i32 (LoadOp addrmode6:$Rn)),
537 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
538 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
541 (i32 (LoadOp addrmode6oneL32:$Rn)),
556 let Inst{4} = Rn{4};
560 let Inst{5} = Rn{4};
561 let Inst{4} = Rn{4};
580 (ins addrmode6:$Rn, am6offset:$Rm,
582 "\\{$Vd[$lane]\\}, $Rn$Rm",
583 "$src = $Vd, $Rn.addr = $wb", []>;
590 let Inst{4} = Rn{4};
594 let Inst{5} = Rn{4};
595 let Inst{4} = Rn{4};
605 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
606 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
609 let Inst{4} = Rn{4};
640 (ins addrmode6:$Rn, am6offset:$Rm,
642 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
643 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
644 let Inst{4} = Rn{4};
674 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
676 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
710 (ins addrmode6:$Rn, am6offset:$Rm,
713 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
714 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
745 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
747 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
750 let Inst{4} = Rn{4};
761 let Inst{5} = Rn{5};
774 let Inst{5} = Rn{5};
784 (ins addrmode6:$Rn, am6offset:$Rm,
787 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
788 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
790 let Inst{4} = Rn{4};
801 let Inst{5} = Rn{5};
813 let Inst{5} = Rn{5};
823 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
824 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
825 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
827 let Inst{4} = Rn{4};
851 (ins addrmode6dup:$Rn), IIC_VLD1dup,
852 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
854 let Inst{4} = Rn{4};
864 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
865 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
866 let Inst{4} = Rn{4};
870 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
871 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
872 let Inst{4} = Rn{4};
890 (ins addrmode6dup:$Rn), IIC_VLD2dup,
891 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
893 let Inst{4} = Rn{4};
912 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
913 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
914 let Inst{4} = Rn{4};
932 (ins addrmode6dup:$Rn), IIC_VLD3dup,
933 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
935 let Inst{4} = Rn{4};
954 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
955 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
956 "$Rn.addr = $wb", []> {
957 let Inst{4} = Rn{4};
976 (ins addrmode6dup:$Rn), IIC_VLD4dup,
977 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
979 let Inst{4} = Rn{4};
984 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
993 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
999 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1000 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1001 "$Rn.addr = $wb", []> {
1002 let Inst{4} = Rn{4};
1007 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1011 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1044 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1045 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1047 let Inst{4} = Rn{4};
1051 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1052 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1054 let Inst{5-4} = Rn{5-4};
1075 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1076 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1077 let Inst{4} = Rn{4};
1081 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1082 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1083 "$Rn.addr = $wb", []> {
1084 let Inst{5-4} = Rn{5-4};
1105 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1106 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1108 let Inst{4} = Rn{4};
1112 (ins addrmode6:$Rn, am6offset:$Rm,
1114 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1115 "$Rn.addr = $wb", []> {
1116 let Inst{4} = Rn{4};
1135 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1136 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1139 let Inst{5-4} = Rn{5-4};
1143 (ins addrmode6:$Rn, am6offset:$Rm,
1145 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1146 "$Rn.addr = $wb", []> {
1147 let Inst{5-4} = Rn{5-4};
1166 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1167 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1169 let Inst{5-4} = Rn{5-4};
1173 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1174 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1177 let Inst{5-4} = Rn{5-4};
1199 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1200 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1201 "$Rn.addr = $wb", []> {
1202 let Inst{5-4} = Rn{5-4};
1206 (ins addrmode6:$Rn, am6offset:$Rm,
1208 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1209 "$Rn.addr = $wb", []> {
1210 let Inst{5-4} = Rn{5-4};
1240 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1241 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1243 let Inst{4} = Rn{4};
1257 (ins addrmode6:$Rn, am6offset:$Rm,
1259 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1260 "$Rn.addr = $wb", []> {
1261 let Inst{4} = Rn{4};
1296 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1297 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1300 let Inst{5-4} = Rn{5-4};
1314 (ins addrmode6:$Rn, am6offset:$Rm,
1316 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1317 "$Rn.addr = $wb", []> {
1318 let Inst{5-4} = Rn{5-4};
1380 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1381 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1382 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1388 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1389 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1390 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1406 let Inst{4} = Rn{5};
1411 let Inst{5-4} = Rn{5-4};
1427 (ins addrmode6:$Rn, am6offset:$Rm,
1429 "\\{$Vd[$lane]\\}, $Rn$Rm",
1430 "$Rn.addr = $wb",
1432 addrmode6:$Rn, am6offset:$Rm))]>;
1446 let Inst{4} = Rn{5};
1451 let Inst{5-4} = Rn{5-4};
1463 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1464 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1467 let Inst{4} = Rn{4};
1487 let Inst{4} = Rn{4};
1491 let Inst{4} = Rn{4};
1504 let Inst{4} = Rn{4};
1534 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1536 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1568 (ins addrmode6:$Rn, am6offset:$Rm,
1571 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1572 "$Rn.addr = $wb", []>;
1601 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1603 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1606 let Inst{4} = Rn{4};
1617 let Inst{5} = Rn{5};
1630 let Inst{5} = Rn{5};
1639 (ins addrmode6:$Rn, am6offset:$Rm,
1642 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1643 "$Rn.addr = $wb", []> {
1644 let Inst{4} = Rn{4};
1655 let Inst{5} = Rn{5};
1667 let Inst{5} = Rn{5};