Lines Matching refs:src3
674 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
677 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
711 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
714 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
745 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
748 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
785 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
788 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1105 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1106 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1113 DPR:$Vd, DPR:$src2, DPR:$src3),
1114 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1135 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1136 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1144 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1145 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1173 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1174 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1207 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1208 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1240 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1241 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1258 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1259 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1296 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1297 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1315 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1316 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1534 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1536 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1569 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1571 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1601 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1603 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1640 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1642 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
3433 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3435 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3441 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3443 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3449 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3452 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3491 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3493 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3499 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3501 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3507 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3509 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3815 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3829 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4402 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4404 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4405 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4407 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4409 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4410 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4411 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4412 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;