Lines Matching refs:DestReg
109 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
148 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
164 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
169 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); in loadRegFromStackSlot()
174 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
182 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
188 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
194 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) in emitT2RegPlusImmediate()
195 .addReg(DestReg) in emitT2RegPlusImmediate()
203 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) in emitT2RegPlusImmediate()
205 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
209 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) in emitT2RegPlusImmediate()
210 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
222 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
224 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg) in emitT2RegPlusImmediate()
233 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { in emitT2RegPlusImmediate()
237 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate()
256 assert(DestReg != ARM::SP && BaseReg != ARM::SP); in emitT2RegPlusImmediate()
276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate()
282 BaseReg = DestReg; in emitT2RegPlusImmediate()