Lines Matching refs:v16i8
60 def v16i8: LoadDFormVec<v16i8>;
92 def v16i8: LoadAFormVec<v16i8>;
124 def v16i8: LoadXFormVec<v16i8>;
172 def v16i8: StoreDFormVec<v16i8>;
202 def v16i8: StoreAFormVec<v16i8>;
234 def v16i8: StoreXFormVec<v16i8>;
267 [(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
271 [(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
469 def v16i8: FSMBIVec<v16i8>;
492 def v16i8_r16: FSMBRegInst<R16C, v16i8>;
493 def v16i8: FSMBVecInst<v16i8>;
599 def v16i8: AVecInst<v16i8>;
1009 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
1043 def v16i8_r32: GBBRegInst<R32C, v16i8>;
1044 def v16i8_r16: GBBRegInst<R16C, v16i8>;
1045 def v16i8: GBBVecInst<v16i8>;
1131 def v16i8: XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
1225 def v16i8: ANDVecInst<v16i8>;
1287 def v16i8: ANDCVecInst<v16i8>;
1299 def v16i8_conv: ANDCVecInst<v16i8, vnot_cell_conv>;
1310 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1311 [(set (v16i8 VECREG:$rT),
1312 (and (v16i8 VECREG:$rA),
1313 (v16i8 v16i8U8Imm:$val)))]>;
1393 def v16i8: ORVecInst<v16i8>;
1427 def : Pat<(v16i8 (SPUprefslot2vec R8C:$rA)),
1445 def : Pat<(i8 (SPUvec2prefslot (v16i8 VECREG:$rA))),
1446 (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>;
1493 def v16i8: LRVecInst<v16i8>;
1524 def v16i8: ORCVecInst<v16i8>;
1545 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1550 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1643 def v16i8: XORVecInst<v16i8>;
1676 def v16i8:
1678 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1725 def v16i8: NANDVecInst<v16i8>;
1755 def v16i8: NORVecInst<v16i8>;
1808 def v16i8: SELBVecInst<v16i8>;
1819 def v16i8_cond: SELBVecCondInst<v16i8>;
1824 def v16i8_vcond: SELBVecCondInst<v16i8>;
1849 def : SPUselbPatVec<v16i8, SELBv16i8>;
1916 def v16i8: EQVVecInst<v16i8>;
1921 def v16i8_1: EQVVecPattern1<v16i8>;
1926 def v16i8_2: EQVVecPattern2<v16i8>;
1931 def v16i8_3: EQVVecPattern3<v16i8>;
1989 def v16i8 : SHUFBVecInst<v16i8, v16i8>;
1990 def v16i8_m32 : SHUFBVecInst<v16i8, v4i32>;
1991 def v8i16 : SHUFBVecInst<v8i16, v16i8>;
1993 def v4i32 : SHUFBVecInst<v4i32, v16i8>;
1995 def v2i64 : SHUFBVecInst<v2i64, v16i8>;
1998 def v4f32 : SHUFBVecInst<v4f32, v16i8>;
2001 def v2f64 : SHUFBVecInst<v2f64, v16i8>;
2124 def v16i8: SHLQBIVecInst<v16i8>;
2149 def v16i8 : SHLQBIIVecInst<v16i8>;
2173 def v16i8: SHLQBYVecInst<v16i8>;
2196 def v16i8: SHLQBYIVecInst<v16i8>;
2223 def v16i8: SHLQBYBIVecInst<v16i8>;
2384 def v16i8: ROTQBYVecInst<v16i8>;
2413 def v16i8: ROTQBYIVecInst<v16i8>;
2436 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2465 def v16i8: ROTQBIVecInst<v16i8>;
2492 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2647 def v16i8: ROTQMBYVecInst<v16i8>;
2682 def v16i8: ROTQMBYIVecInst<v16i8>;
2712 def v16i8: ROTQMBYBIVecInst<v16i8>;
2741 def v16i8: ROTQMBIVecInst<v16i8>;
2776 def v16i8: ROTQMBIIVecInst<v16i8>;
2933 def v16i8 :
2935 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2949 def v16i8 :
2951 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
3021 def v16i8 :
3023 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3037 def v16i8 :
3039 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
3118 def v16i8 :
3120 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3134 def v16i8 :
3136 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
4211 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
4212 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
4213 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
4214 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
4215 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
4217 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
4223 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
4229 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
4235 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
4241 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
4247 def : Pat<(i128 (bitconvert (v16i8 VECREG:$src))),
4260 def : Pat<(v16i8 (bitconvert (i128 GPRC:$src))),
4261 (v16i8 (COPY_TO_REGCLASS GPRC:$src, VECREG))>;