Lines Matching refs:cycle
18 // The instruction takes one cycle to execute in each of the stages. The
22 [ InstrStage<1,[IF]> // one cycle in fetch stage
23 , InstrStage<1,[ID]> // one cycle in decode stage
24 , InstrStage<1,[EX]>], // one cycle in execute stage
26 , 1 // first operand read after one cycle
27 , 1 ]>, // second operand read after one cycle
31 // operand. The instruction takes one cycle to execute in each of the
36 [ InstrStage<1,[IF]> // one cycle in fetch stage
37 , InstrStage<1,[ID]> // one cycle in decode stage
40 , 1 // first operand read after one cycle
41 , 1 ]>, // second operand read after one cycle
44 // operands. The instruction takes one cycle to execute in each the pipeline
49 [ InstrStage<1,[IF]> // one cycle in fetch stage
50 , InstrStage<1,[ID]> // one cycle in decode stage
53 , 1 // first operand read after one cycle
54 , 1 ]>, // second operand read after one cycle
58 // The instruction takes one cycle to execute in each of the pipeline stages
63 [ InstrStage<1,[IF]> // one cycle in fetch stage
64 , InstrStage<1,[ID]> // one cycle in decode stage
67 , 1 // first operand read after one cycle
68 , 1 ]>, // second operand read after one cycle
71 // one cycle to execute in each of the pipeline stages. The source operand is
74 [ InstrStage<1,[IF]> // one cycle in fetch stage
75 , InstrStage<1,[ID]> // one cycle in decode stage
76 , InstrStage<1,[EX]>], // one cycle in execute stage
77 [ 1 ]>, // first operand read after one cycle
80 // instruction takes one cycle to execute in each of the pipeline stages. The
83 [ InstrStage<1,[IF]> // one cycle in fetch stage
84 , InstrStage<1,[ID]> // one cycle in decode stage
85 , InstrStage<1,[EX]>], // one cycle in execute stage
86 [ 1 // first operand read after one cycle
87 , 1 ]>, // second operand read after one cycle
90 // operand register. The instruction takes one cycle to execute in each of
94 [ InstrStage<1,[IF]> // one cycle in fetch stage
95 , InstrStage<1,[ID]> // one cycle in decode stage
96 , InstrStage<1,[EX]>], // one cycle in execute stage
98 , 1 ]>, // first operand read after one cycle
101 // instruction takes one cycle to execute in each of the pipeline stages
105 [ InstrStage<1,[IF]> // one cycle in fetch stage
106 , InstrStage<1,[ID]> // one cycle in decode stage
108 [ 1 // first operand read after one cycle
109 , 1 ]>, // second operand read after one cycle
112 // operand registers. The instruction takes one cycle to execute in each of
117 [ InstrStage<1,[IF]> // one cycle in fetch stage
118 , InstrStage<1,[ID]> // one cycle in decode stage
121 , 1 // first operand read after one cycle
122 , 1 ]>, // second operand read after one cycle
125 // source operand registers. The instruction takes one cycle to execute in
130 [ InstrStage<1,[IF]> // one cycle in fetch stage
131 , InstrStage<1,[ID]> // one cycle in decode stage
132 , InstrStage<30,[EX]>], // one cycle in execute stage
134 , 1 // first operand read after one cycle
135 , 1 ]>, // second operand read after one cycle
138 // register and one source operand register. The instruction takes one cycle
143 [ InstrStage<1,[IF]> // one cycle in fetch stage
144 , InstrStage<1,[ID]> // one cycle in decode stage
147 , 1 ]>, // first operand read after one cycle
150 // register and one source operand register. The instruction takes one cycle
155 [ InstrStage<1,[IF]> // one cycle in fetch stage
156 , InstrStage<1,[ID]> // one cycle in decode stage
159 , 1 ]>, // first operand read after one cycle
162 // one source operand register. The instruction takes one cycle to execute in
167 [ InstrStage<1,[IF]> // one cycle in fetch stage
168 , InstrStage<1,[ID]> // one cycle in decode stage
171 , 1 ]>, // first operand read after one cycle
174 // two source operand registers. The instruction takes one cycle to execute
179 [ InstrStage<1,[IF]> // one cycle in fetch stage
180 , InstrStage<1,[ID]> // one cycle in decode stage
183 , 1 // first operand read after one cycle
184 , 1 ]>, // second operand read after one cycle
187 // destination register. The instruction takes one cycle to execute in each
192 [ InstrStage<1,[IF]> // one cycle in fetch stage
193 , InstrStage<1,[ID]> // one cycle in decode stage
196 , 1 ]>, // first operand read after one cycle
200 // produced by the instruction. The instruction takes one cycle to execute in
204 [ InstrStage<1,[IF]> // one cycle in fetch stage
205 , InstrStage<1,[ID]> // one cycle in decode stage
207 [ 1 // first operand read after one cycle
208 , 1 ]>, // second operand read after one cycle
212 // produced by the instruction. The instruction takes one cycle to execute in
216 [ InstrStage<1,[IF]> // one cycle in fetch stage
217 , InstrStage<1,[ID]> // one cycle in decode stage
219 [ 1 // first operand read after one cycle
220 , 1 // second operand read after one cycle
221 , 1 ]>, // third operand read after one cycle
225 // operand. The instruction takes one cycle to execute in each of the
230 [ InstrStage<1,[IF]> // one cycle in fetch stage
231 , InstrStage<1,[ID]> // one cycle in decode stage
234 , 1 // second operand read after one cycle
235 , 1 ]> // third operand read after one cycle