Lines Matching refs:cycle
18 // The instruction takes one cycle to execute in each of the stages. The
22 [ InstrStage<1,[IF]> // one cycle in fetch stage
23 , InstrStage<1,[ID]> // one cycle in decode stage
24 , InstrStage<1,[EX]> // one cycle in execute stage
25 , InstrStage<1,[MA]> // one cycle in memory access stage
26 , InstrStage<1,[WB]>], // one cycle in write back stage
28 , 1 // first operand read after one cycle
29 , 1 ]>, // second operand read after one cycle
33 // operand. The instruction takes one cycle to execute in each of the
37 [ InstrStage<1,[IF]> // one cycle in fetch stage
38 , InstrStage<1,[ID]> // one cycle in decode stage
39 , InstrStage<1,[EX]> // one cycle in execute stage
40 , InstrStage<1,[MA]> // one cycle in memory access stage
41 , InstrStage<1,[WB]>], // one cycle in write back stage
43 , 1 // first operand read after one cycle
44 , 1 ]>, // second operand read after one cycle
47 // operands. The instruction takes one cycle to execute in each the pipeline
52 [ InstrStage<1,[IF]> // one cycle in fetch stage
53 , InstrStage<1,[ID]> // one cycle in decode stage
54 , InstrStage<1,[EX]> // one cycle in execute stage
56 , InstrStage<1,[WB]>], // one cycle in write back stage
58 , 1 // first operand read after one cycle
59 , 1 ]>, // second operand read after one cycle
63 // The instruction takes one cycle to execute in each of the pipeline stages.
67 [ InstrStage<1,[IF]> // one cycle in fetch stage
68 , InstrStage<1,[ID]> // one cycle in decode stage
69 , InstrStage<1,[EX]> // one cycle in execute stage
70 , InstrStage<1,[MA]> // one cycle in memory access stage
71 , InstrStage<1,[WB]>], // one cycle in write back stage
73 , 1 // first operand read after one cycle
74 , 1 ]>, // second operand read after one cycle
77 // one cycle to execute in each of the pipeline stages. The source operand is
80 [ InstrStage<1,[IF]> // one cycle in fetch stage
81 , InstrStage<1,[ID]> // one cycle in decode stage
82 , InstrStage<1,[EX]> // one cycle in execute stage
83 , InstrStage<1,[MA]> // one cycle in memory access stage
84 , InstrStage<1,[WB]>], // one cycle in write back stage
85 [ 1 ]>, // first operand read after one cycle
88 // instruction takes one cycle to execute in each of the pipeline stages. The
91 [ InstrStage<1,[IF]> // one cycle in fetch stage
92 , InstrStage<1,[ID]> // one cycle in decode stage
93 , InstrStage<1,[EX]> // one cycle in execute stage
94 , InstrStage<1,[MA]> // one cycle in memory access stage
95 , InstrStage<1,[WB]>], // one cycle in write back stage
96 [ 1 // first operand read after one cycle
97 , 1 ]>, // second operand read after one cycle
100 // operand register. The instruction takes one cycle to execute in each of
104 [ InstrStage<1,[IF]> // one cycle in fetch stage
105 , InstrStage<1,[ID]> // one cycle in decode stage
106 , InstrStage<1,[EX]> // one cycle in execute stage
107 , InstrStage<1,[MA]> // one cycle in memory access stage
108 , InstrStage<1,[WB]>], // one cycle in write back stage
110 , 1 ]>, // first operand read after one cycle
113 // instruction takes one cycle to execute in each of the pipeline stages
117 [ InstrStage<1,[IF]> // one cycle in fetch stage
118 , InstrStage<1,[ID]> // one cycle in decode stage
119 , InstrStage<1,[EX]> // one cycle in execute stage
121 , InstrStage<1,[WB]>], // one cycle in write back stage
122 [ 1 // first operand read after one cycle
123 , 1 ]>, // second operand read after one cycle
126 // operand registers. The instruction takes one cycle to execute in each of
131 [ InstrStage<1,[IF]> // one cycle in fetch stage
132 , InstrStage<1,[ID]> // one cycle in decode stage
133 , InstrStage<1,[EX]> // one cycle in execute stage
135 , InstrStage<1,[WB]>], // one cycle in write back stage
137 , 1 // first operand read after one cycle
138 , 1 ]>, // second operand read after one cycle
141 // source operand registers. The instruction takes one cycle to execute in
146 [ InstrStage<1,[IF]> // one cycle in fetch stage
147 , InstrStage<1,[ID]> // one cycle in decode stage
148 , InstrStage<1,[EX]> // one cycle in execute stage
150 , InstrStage<1,[WB]>], // one cycle in write back stage
152 , 1 // first operand read after one cycle
153 , 1 ]>, // second operand read after one cycle
156 // register and one source operand register. The instruction takes one cycle
161 [ InstrStage<1,[IF]> // one cycle in fetch stage
162 , InstrStage<1,[ID]> // one cycle in decode stage
163 , InstrStage<1,[EX]> // one cycle in execute stage
165 , InstrStage<1,[WB]>], // one cycle in write back stage
167 , 1 ]>, // first operand read after one cycle
170 // register and one source operand register. The instruction takes one cycle
175 [ InstrStage<1,[IF]> // one cycle in fetch stage
176 , InstrStage<1,[ID]> // one cycle in decode stage
177 , InstrStage<1,[EX]> // one cycle in execute stage
179 , InstrStage<1,[WB]>], // one cycle in write back stage
181 , 1 ]>, // first operand read after one cycle
184 // one source operand register. The instruction takes one cycle to execute in
189 [ InstrStage<1,[IF]> // one cycle in fetch stage
190 , InstrStage<1,[ID]> // one cycle in decode stage
191 , InstrStage<1,[EX]> // one cycle in execute stage
193 , InstrStage<1,[WB]>], // one cycle in write back stage
195 , 1 ]>, // first operand read after one cycle
198 // two source operand registers. The instruction takes one cycle to execute
202 [ InstrStage<1,[IF]> // one cycle in fetch stage
203 , InstrStage<1,[ID]> // one cycle in decode stage
204 , InstrStage<1,[EX]> // one cycle in execute stage
205 , InstrStage<1,[MA]> // one cycle in memory access stage
206 , InstrStage<1,[WB]>], // one cycle in write back stage
208 , 1 // first operand read after one cycle
209 , 1 ]>, // second operand read after one cycle
212 // destination register. The instruction takes one cycle to execute in each
216 [ InstrStage<1,[IF]> // one cycle in fetch stage
217 , InstrStage<1,[ID]> // one cycle in decode stage
218 , InstrStage<1,[EX]> // one cycle in execute stage
219 , InstrStage<1,[MA]> // one cycle in memory access stage
220 , InstrStage<1,[WB]>], // one cycle in write back stage
222 , 1 ]>, // first operand read after one cycle
226 // produced by the instruction. The instruction takes one cycle to execute in
230 [ InstrStage<1,[IF]> // one cycle in fetch stage
231 , InstrStage<1,[ID]> // one cycle in decode stage
232 , InstrStage<1,[EX]> // one cycle in execute stage
233 , InstrStage<1,[MA]> // one cycle in memory access stage
234 , InstrStage<1,[WB]>], // one cycle in write back stage
235 [ 1 // first operand read after one cycle
236 , 1 ]>, // second operand read after one cycle
240 // produced by the instruction. The instruction takes one cycle to execute in
244 [ InstrStage<1,[IF]> // one cycle in fetch stage
245 , InstrStage<1,[ID]> // one cycle in decode stage
246 , InstrStage<1,[EX]> // one cycle in execute stage
247 , InstrStage<1,[MA]> // one cycle in memory access stage
248 , InstrStage<1,[WB]>], // one cycle in write back stage
249 [ 1 // first operand read after one cycle
250 , 1 // second operand read after one cycle
251 , 1 ]>, // third operand read after one cycle
255 // operand. The instruction takes one cycle to execute in each of the
259 [ InstrStage<1,[IF]> // one cycle in fetch stage
260 , InstrStage<1,[ID]> // one cycle in decode stage
261 , InstrStage<1,[EX]> // one cycle in execute stage
262 , InstrStage<1,[MA]> // one cycle in memory access stage
263 , InstrStage<1,[WB]>], // one cycle in write back stage
265 , 1 // second operand read after one cycle
266 , 1 ]> // third operand read after one cycle