Lines Matching refs:dst
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
127 [(set GR8:$dst,
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
131 [(set GR16:$dst,
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
136 [(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>;
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
139 [(set GR16:$dst, (MSP430shl GR16:$src, GR8:$cnt))]>;
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
142 [(set GR8:$dst, (MSP430sra GR8:$src, GR8:$cnt))]>;
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
145 [(set GR16:$dst, (MSP430sra GR16:$src, GR8:$cnt))]>;
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
148 [(set GR8:$dst, (MSP430srl GR8:$src, GR8:$cnt))]>;
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
151 [(set GR16:$dst, (MSP430srl GR16:$src, GR8:$cnt))]>;
177 def JMP : CJForm<0, 0, (outs), (ins jmptarget:$dst),
178 "jmp\t$dst",
179 [(br bb:$dst)]>;
197 (outs), (ins jmptarget:$dst, cc:$cc),
198 "j$cc\t$dst",
199 [(MSP430brcc bb:$dst, imm:$cc)]>;
213 (outs), (ins i16imm:$dst, variable_ops),
214 "call\t$dst", [(MSP430call imm:$dst)]>;
216 (outs), (ins GR16:$dst, variable_ops),
217 "call\t$dst", [(MSP430call GR16:$dst)]>;
219 (outs), (ins memsrc:$dst, variable_ops),
220 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
243 (outs GR8:$dst), (ins GR8:$src),
244 "mov.b\t{$src, $dst}",
247 (outs GR16:$dst), (ins GR16:$src),
248 "mov.w\t{$src, $dst}",
255 (outs GR8:$dst), (ins i8imm:$src),
256 "mov.b\t{$src, $dst}",
257 [(set GR8:$dst, imm:$src)]>;
259 (outs GR16:$dst), (ins i16imm:$src),
260 "mov.w\t{$src, $dst}",
261 [(set GR16:$dst, imm:$src)]>;
266 (outs GR8:$dst), (ins memsrc:$src),
267 "mov.b\t{$src, $dst}",
268 [(set GR8:$dst, (load addr:$src))]>;
270 (outs GR16:$dst), (ins memsrc:$src),
271 "mov.w\t{$src, $dst}",
272 [(set GR16:$dst, (load addr:$src))]>;
276 (outs GR16:$dst), (ins GR8:$src),
277 "mov.b\t{$src, $dst}",
278 [(set GR16:$dst, (zext GR8:$src))]>;
280 (outs GR16:$dst), (ins memsrc:$src),
281 "mov.b\t{$src, $dst}",
282 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
286 (outs GR8:$dst, GR16:$base_wb), (ins GR16:$base),
287 "mov.b\t{@$base+, $dst}", []>;
289 (outs GR16:$dst, GR16:$base_wb), (ins GR16:$base),
290 "mov.w\t{@$base+, $dst}", []>;
309 (outs), (ins memdst:$dst, i8imm:$src),
310 "mov.b\t{$src, $dst}",
311 [(store (i8 imm:$src), addr:$dst)]>;
313 (outs), (ins memdst:$dst, i16imm:$src),
314 "mov.w\t{$src, $dst}",
315 [(store (i16 imm:$src), addr:$dst)]>;
318 (outs), (ins memdst:$dst, GR8:$src),
319 "mov.b\t{$src, $dst}",
320 [(store GR8:$src, addr:$dst)]>;
322 (outs), (ins memdst:$dst, GR16:$src),
323 "mov.w\t{$src, $dst}",
324 [(store GR16:$src, addr:$dst)]>;
327 (outs), (ins memdst:$dst, memsrc:$src),
328 "mov.b\t{$src, $dst}",
329 [(store (i8 (load addr:$src)), addr:$dst)]>;
331 (outs), (ins memdst:$dst, memsrc:$src),
332 "mov.w\t{$src, $dst}",
333 [(store (i16 (load addr:$src)), addr:$dst)]>;
338 let Constraints = "$src = $dst" in {
345 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
346 "add.b\t{$src2, $dst}",
347 [(set GR8:$dst, (add GR8:$src, GR8:$src2)),
350 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
351 "add.w\t{$src2, $dst}",
352 [(set GR16:$dst, (add GR16:$src, GR16:$src2)),
357 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
358 "add.b\t{$src2, $dst}",
359 [(set GR8:$dst, (add GR8:$src, (load addr:$src2))),
362 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
363 "add.w\t{$src2, $dst}",
364 [(set GR16:$dst, (add GR16:$src, (load addr:$src2))),
368 Constraints = "$base = $base_wb, $src = $dst" in {
370 (outs GR8:$dst, GR16:$base_wb),
372 "add.b\t{@$base+, $dst}", []>;
374 (outs GR16:$dst, GR16:$base_wb),
376 "add.w\t{@$base+, $dst}", []>;
381 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
382 "add.b\t{$src2, $dst}",
383 [(set GR8:$dst, (add GR8:$src, imm:$src2)),
386 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
387 "add.w\t{$src2, $dst}",
388 [(set GR16:$dst, (add GR16:$src, imm:$src2)),
393 (outs), (ins memdst:$dst, GR8:$src),
394 "add.b\t{$src, $dst}",
395 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
398 (outs), (ins memdst:$dst, GR16:$src),
399 "add.w\t{$src, $dst}",
400 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
404 (outs), (ins memdst:$dst, i8imm:$src),
405 "add.b\t{$src, $dst}",
406 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
409 (outs), (ins memdst:$dst, i16imm:$src),
410 "add.w\t{$src, $dst}",
411 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
415 (outs), (ins memdst:$dst, memsrc:$src),
416 "add.b\t{$src, $dst}",
417 [(store (add (load addr:$dst),
418 (i8 (load addr:$src))), addr:$dst),
421 (outs), (ins memdst:$dst, memsrc:$src),
422 "add.w\t{$src, $dst}",
423 [(store (add (load addr:$dst),
424 (i16 (load addr:$src))), addr:$dst),
432 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
433 "addc.b\t{$src2, $dst}",
434 [(set GR8:$dst, (adde GR8:$src, GR8:$src2)),
437 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
438 "addc.w\t{$src2, $dst}",
439 [(set GR16:$dst, (adde GR16:$src, GR16:$src2)),
444 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
445 "addc.b\t{$src2, $dst}",
446 [(set GR8:$dst, (adde GR8:$src, imm:$src2)),
449 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
450 "addc.w\t{$src2, $dst}",
451 [(set GR16:$dst, (adde GR16:$src, imm:$src2)),
455 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
456 "addc.b\t{$src2, $dst}",
457 [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))),
460 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
461 "addc.w\t{$src2, $dst}",
462 [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))),
467 (outs), (ins memdst:$dst, GR8:$src),
468 "addc.b\t{$src, $dst}",
469 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
472 (outs), (ins memdst:$dst, GR16:$src),
473 "addc.w\t{$src, $dst}",
474 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
478 (outs), (ins memdst:$dst, i8imm:$src),
479 "addc.b\t{$src, $dst}",
480 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
483 (outs), (ins memdst:$dst, i16imm:$src),
484 "addc.w\t{$src, $dst}",
485 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
489 (outs), (ins memdst:$dst, memsrc:$src),
490 "addc.b\t{$src, $dst}",
491 [(store (adde (load addr:$dst),
492 (i8 (load addr:$src))), addr:$dst),
495 (outs), (ins memdst:$dst, memsrc:$src),
496 "addc.w\t{$src, $dst}",
497 [(store (adde (load addr:$dst),
498 (i16 (load addr:$src))), addr:$dst),
506 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
507 "and.b\t{$src2, $dst}",
508 [(set GR8:$dst, (and GR8:$src, GR8:$src2)),
511 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
512 "and.w\t{$src2, $dst}",
513 [(set GR16:$dst, (and GR16:$src, GR16:$src2)),
518 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
519 "and.b\t{$src2, $dst}",
520 [(set GR8:$dst, (and GR8:$src, imm:$src2)),
523 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
524 "and.w\t{$src2, $dst}",
525 [(set GR16:$dst, (and GR16:$src, imm:$src2)),
529 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
530 "and.b\t{$src2, $dst}",
531 [(set GR8:$dst, (and GR8:$src, (load addr:$src2))),
534 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
535 "and.w\t{$src2, $dst}",
536 [(set GR16:$dst, (and GR16:$src, (load addr:$src2))),
540 Constraints = "$base = $base_wb, $src = $dst" in {
542 (outs GR8:$dst, GR16:$base_wb),
544 "and.b\t{@$base+, $dst}", []>;
546 (outs GR16:$dst, GR16:$base_wb),
548 "and.w\t{@$base+, $dst}", []>;
553 (outs), (ins memdst:$dst, GR8:$src),
554 "and.b\t{$src, $dst}",
555 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
558 (outs), (ins memdst:$dst, GR16:$src),
559 "and.w\t{$src, $dst}",
560 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
564 (outs), (ins memdst:$dst, i8imm:$src),
565 "and.b\t{$src, $dst}",
566 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
569 (outs), (ins memdst:$dst, i16imm:$src),
570 "and.w\t{$src, $dst}",
571 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
575 (outs), (ins memdst:$dst, memsrc:$src),
576 "and.b\t{$src, $dst}",
577 [(store (and (load addr:$dst),
578 (i8 (load addr:$src))), addr:$dst),
581 (outs), (ins memdst:$dst, memsrc:$src),
582 "and.w\t{$src, $dst}",
583 [(store (and (load addr:$dst),
584 (i16 (load addr:$src))), addr:$dst),
590 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
591 "bis.b\t{$src2, $dst}",
592 [(set GR8:$dst, (or GR8:$src, GR8:$src2))]>;
594 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
595 "bis.w\t{$src2, $dst}",
596 [(set GR16:$dst, (or GR16:$src, GR16:$src2))]>;
600 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
601 "bis.b\t{$src2, $dst}",
602 [(set GR8:$dst, (or GR8:$src, imm:$src2))]>;
604 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
605 "bis.w\t{$src2, $dst}",
606 [(set GR16:$dst, (or GR16:$src, imm:$src2))]>;
609 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
610 "bis.b\t{$src2, $dst}",
611 [(set GR8:$dst, (or GR8:$src, (load addr:$src2)))]>;
613 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
614 "bis.w\t{$src2, $dst}",
615 [(set GR16:$dst, (or GR16:$src, (load addr:$src2)))]>;
618 Constraints = "$base = $base_wb, $src = $dst" in {
620 (outs GR8:$dst, GR16:$base_wb),
622 "bis.b\t{@$base+, $dst}", []>;
624 (outs GR16:$dst, GR16:$base_wb),
626 "bis.w\t{@$base+, $dst}", []>;
631 (outs), (ins memdst:$dst, GR8:$src),
632 "bis.b\t{$src, $dst}",
633 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
635 (outs), (ins memdst:$dst, GR16:$src),
636 "bis.w\t{$src, $dst}",
637 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
640 (outs), (ins memdst:$dst, i8imm:$src),
641 "bis.b\t{$src, $dst}",
642 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
644 (outs), (ins memdst:$dst, i16imm:$src),
645 "bis.w\t{$src, $dst}",
646 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
649 (outs), (ins memdst:$dst, memsrc:$src),
650 "bis.b\t{$src, $dst}",
651 [(store (or (i8 (load addr:$dst)),
652 (i8 (load addr:$src))), addr:$dst)]>;
654 (outs), (ins memdst:$dst, memsrc:$src),
655 "bis.w\t{$src, $dst}",
656 [(store (or (i16 (load addr:$dst)),
657 (i16 (load addr:$src))), addr:$dst)]>;
662 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
663 "bic.b\t{$src2, $dst}",
664 [(set GR8:$dst, (and GR8:$src, (not GR8:$src2)))]>;
666 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
667 "bic.w\t{$src2, $dst}",
668 [(set GR16:$dst, (and GR16:$src, (not GR16:$src2)))]>;
671 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
672 "bic.b\t{$src2, $dst}",
673 [(set GR8:$dst, (and GR8:$src, (not (i8 (load addr:$src2)))))]>;
675 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
676 "bic.w\t{$src2, $dst}",
677 [(set GR16:$dst, (and GR16:$src, (not (i16 (load addr:$src2)))))]>;
681 (outs), (ins memdst:$dst, GR8:$src),
682 "bic.b\t{$src, $dst}",
683 [(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>;
685 (outs), (ins memdst:$dst, GR16:$src),
686 "bic.w\t{$src, $dst}",
687 [(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>;
690 (outs), (ins memdst:$dst, memsrc:$src),
691 "bic.b\t{$src, $dst}",
692 [(store (and (load addr:$dst),
693 (not (i8 (load addr:$src)))), addr:$dst)]>;
695 (outs), (ins memdst:$dst, memsrc:$src),
696 "bic.w\t{$src, $dst}",
697 [(store (and (load addr:$dst),
698 (not (i16 (load addr:$src)))), addr:$dst)]>;
703 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
704 "xor.b\t{$src2, $dst}",
705 [(set GR8:$dst, (xor GR8:$src, GR8:$src2)),
708 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
709 "xor.w\t{$src2, $dst}",
710 [(set GR16:$dst, (xor GR16:$src, GR16:$src2)),
715 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
716 "xor.b\t{$src2, $dst}",
717 [(set GR8:$dst, (xor GR8:$src, imm:$src2)),
720 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
721 "xor.w\t{$src2, $dst}",
722 [(set GR16:$dst, (xor GR16:$src, imm:$src2)),
726 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
727 "xor.b\t{$src2, $dst}",
728 [(set GR8:$dst, (xor GR8:$src, (load addr:$src2))),
731 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
732 "xor.w\t{$src2, $dst}",
733 [(set GR16:$dst, (xor GR16:$src, (load addr:$src2))),
737 Constraints = "$base = $base_wb, $src = $dst" in {
739 (outs GR8:$dst, GR16:$base_wb),
741 "xor.b\t{@$base+, $dst}", []>;
743 (outs GR16:$dst, GR16:$base_wb),
745 "xor.w\t{@$base+, $dst}", []>;
750 (outs), (ins memdst:$dst, GR8:$src),
751 "xor.b\t{$src, $dst}",
752 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
755 (outs), (ins memdst:$dst, GR16:$src),
756 "xor.w\t{$src, $dst}",
757 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
761 (outs), (ins memdst:$dst, i8imm:$src),
762 "xor.b\t{$src, $dst}",
763 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
766 (outs), (ins memdst:$dst, i16imm:$src),
767 "xor.w\t{$src, $dst}",
768 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
772 (outs), (ins memdst:$dst, memsrc:$src),
773 "xor.b\t{$src, $dst}",
774 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
777 (outs), (ins memdst:$dst, memsrc:$src),
778 "xor.w\t{$src, $dst}",
779 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
785 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
786 "sub.b\t{$src2, $dst}",
787 [(set GR8:$dst, (sub GR8:$src, GR8:$src2)),
790 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
791 "sub.w\t{$src2, $dst}",
792 [(set GR16:$dst, (sub GR16:$src, GR16:$src2)),
796 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
797 "sub.b\t{$src2, $dst}",
798 [(set GR8:$dst, (sub GR8:$src, imm:$src2)),
801 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
802 "sub.w\t{$src2, $dst}",
803 [(set GR16:$dst, (sub GR16:$src, imm:$src2)),
807 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
808 "sub.b\t{$src2, $dst}",
809 [(set GR8:$dst, (sub GR8:$src, (load addr:$src2))),
812 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
813 "sub.w\t{$src2, $dst}",
814 [(set GR16:$dst, (sub GR16:$src, (load addr:$src2))),
818 Constraints = "$base = $base_wb, $src = $dst" in {
820 (outs GR8:$dst, GR16:$base_wb),
822 "sub.b\t{@$base+, $dst}", []>;
824 (outs GR16:$dst, GR16:$base_wb),
826 "sub.w\t{@$base+, $dst}", []>;
831 (outs), (ins memdst:$dst, GR8:$src),
832 "sub.b\t{$src, $dst}",
833 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
836 (outs), (ins memdst:$dst, GR16:$src),
837 "sub.w\t{$src, $dst}",
838 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
842 (outs), (ins memdst:$dst, i8imm:$src),
843 "sub.b\t{$src, $dst}",
844 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
847 (outs), (ins memdst:$dst, i16imm:$src),
848 "sub.w\t{$src, $dst}",
849 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
853 (outs), (ins memdst:$dst, memsrc:$src),
854 "sub.b\t{$src, $dst}",
855 [(store (sub (load addr:$dst),
856 (i8 (load addr:$src))), addr:$dst),
859 (outs), (ins memdst:$dst, memsrc:$src),
860 "sub.w\t{$src, $dst}",
861 [(store (sub (load addr:$dst),
862 (i16 (load addr:$src))), addr:$dst),
868 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
869 "subc.b\t{$src2, $dst}",
870 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
873 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
874 "subc.w\t{$src2, $dst}",
875 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
879 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
880 "subc.b\t{$src2, $dst}",
881 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
884 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
885 "subc.w\t{$src2, $dst}",
886 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
890 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
891 "subc.b\t{$src2, $dst}",
892 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
895 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
896 "subc.w\t{$src2, $dst}",
897 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
902 (outs), (ins memdst:$dst, GR8:$src),
903 "subc.b\t{$src, $dst}",
904 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
907 (outs), (ins memdst:$dst, GR16:$src),
908 "subc.w\t{$src, $dst}",
909 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
913 (outs), (ins memdst:$dst, i8imm:$src),
914 "subc.b\t{$src, $dst}",
915 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
918 (outs), (ins memdst:$dst, i16imm:$src),
919 "subc.w\t{$src, $dst}",
920 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
924 (outs), (ins memdst:$dst, memsrc:$src),
925 "subc.b\t{$src, $dst}",
926 [(store (sube (load addr:$dst),
927 (i8 (load addr:$src))), addr:$dst),
930 (outs), (ins memdst:$dst, memsrc:$src),
931 "subc.w\t{$src, $dst}",
932 [(store (sube (load addr:$dst),
933 (i16 (load addr:$src))), addr:$dst),
941 (outs GR8:$dst), (ins GR8:$src),
942 "rra.b\t$dst",
943 [(set GR8:$dst, (MSP430rra GR8:$src)),
946 (outs GR16:$dst), (ins GR16:$src),
947 "rra.w\t$dst",
948 [(set GR16:$dst, (MSP430rra GR16:$src)),
952 (outs GR8:$dst), (ins GR8:$src),
953 "rla.b\t$dst",
954 [(set GR8:$dst, (MSP430rla GR8:$src)),
957 (outs GR16:$dst), (ins GR16:$src),
958 "rla.w\t$dst",
959 [(set GR16:$dst, (MSP430rla GR16:$src)),
962 def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
964 "rrc.b\t$dst",
965 [(set GR8:$dst, (MSP430rrc GR8:$src)),
967 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
969 "rrc.w\t$dst",
970 [(set GR16:$dst, (MSP430rrc GR16:$src)),
975 (outs GR16:$dst), (ins GR16:$src),
976 "sxt\t$dst",
977 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
983 (outs GR16:$dst), (ins GR16:$src),
984 "mov.b\t{$src, $dst}",
985 [(set GR16:$dst, (zext (trunc GR16:$src)))]>;
989 (outs GR16:$dst), (ins GR16:$src),
990 "swpb\t$dst",
991 [(set GR16:$dst, (bswap GR16:$src))]>;
993 } // Constraints = "$src = $dst"
1138 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
1139 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
1140 def : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>;
1149 def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
1150 (MOV16mi addr:$dst, tglobaladdr:$src)>;
1151 def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
1152 (MOV16mi addr:$dst, texternalsym:$src)>;
1153 def : Pat<(store (i16 (MSP430Wrapper tblockaddress:$src)), addr:$dst),
1154 (MOV16mi addr:$dst, tblockaddress:$src)>;
1157 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
1158 (CALLi tglobaladdr:$dst)>;
1159 def : Pat<(MSP430call (i16 texternalsym:$dst)),
1160 (CALLi texternalsym:$dst)>;
1169 def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
1170 (ADD16mr addr:$dst, GR16:$src)>;
1171 def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
1172 (ADD16mm addr:$dst, addr:$src)>;
1180 def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
1181 (ADD8mr addr:$dst, GR8:$src)>;
1182 def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
1183 (ADD8mm addr:$dst, addr:$src)>;
1191 def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
1192 (SUB16mr addr:$dst, GR16:$src)>;
1193 def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
1194 (SUB16mm addr:$dst, addr:$src)>;
1202 def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
1203 (SUB8mr addr:$dst, GR8:$src)>;
1204 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
1205 (SUB8mm addr:$dst, addr:$src)>;