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Lines Matching refs:def

38 def sub_fpeven : SubRegIndex;
39 def sub_fpodd : SubRegIndex;
59 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
60 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
61 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
62 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
63 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
64 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
65 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
66 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
67 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
68 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
69 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
70 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
71 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
72 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
73 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
74 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
75 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
76 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
77 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
78 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
79 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
80 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
81 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
82 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
83 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
84 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
85 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
86 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
87 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
88 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
89 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
90 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
93 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
94 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
95 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
96 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
97 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
98 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
99 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
100 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
101 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
102 def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
103 def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
104 def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
105 def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
106 def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
107 def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
108 def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
109 def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
110 def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
111 def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
112 def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
113 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
114 def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
115 def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
116 def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
117 def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
118 def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
119 def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
120 def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
121 def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
122 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
123 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
124 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
128 def D0 : AFPR< 0, "F0", [F0, F1]>;
129 def D1 : AFPR< 2, "F2", [F2, F3]>;
130 def D2 : AFPR< 4, "F4", [F4, F5]>;
131 def D3 : AFPR< 6, "F6", [F6, F7]>;
132 def D4 : AFPR< 8, "F8", [F8, F9]>;
133 def D5 : AFPR<10, "F10", [F10, F11]>;
134 def D6 : AFPR<12, "F12", [F12, F13]>;
135 def D7 : AFPR<14, "F14", [F14, F15]>;
136 def D8 : AFPR<16, "F16", [F16, F17]>;
137 def D9 : AFPR<18, "F18", [F18, F19]>;
138 def D10 : AFPR<20, "F20", [F20, F21]>;
139 def D11 : AFPR<22, "F22", [F22, F23]>;
140 def D12 : AFPR<24, "F24", [F24, F25]>;
141 def D13 : AFPR<26, "F26", [F26, F27]>;
142 def D14 : AFPR<28, "F28", [F28, F29]>;
143 def D15 : AFPR<30, "F30", [F30, F31]>;
146 def HI : Register<"hi">, DwarfRegNum<[64]>;
147 def LO : Register<"lo">, DwarfRegNum<[65]>;
150 def FCR31 : Register<"31">;
153 def HWR29 : Register<"29">;
160 def CPURegs : RegisterClass<"Mips", [i32], 32, (add
177 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
179 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
192 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>;
195 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
198 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;