Lines Matching refs:dst
29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
31 [(set FP32:$dst,
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
35 [(set FP64:$dst,
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
45 "lzer\t{$dst}",
46 [(set FP32:$dst, fpimm0)]>;
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
48 "lzdr\t{$dst}",
49 [(set FP64:$dst, fpimm0)]>;
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
54 "ler\t{$dst, $src}",
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
57 "ldr\t{$dst, $src}",
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
63 "le\t{$dst, $src}",
64 [(set FP32:$dst, (load rriaddr12:$src))]>;
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
66 "ley\t{$dst, $src}",
67 [(set FP32:$dst, (load rriaddr:$src))]>;
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
69 "ld\t{$dst, $src}",
70 [(set FP64:$dst, (load rriaddr12:$src))]>;
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
72 "ldy\t{$dst, $src}",
73 [(set FP64:$dst, (load rriaddr:$src))]>;
76 def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
77 "ste\t{$src, $dst}",
78 [(store FP32:$src, rriaddr12:$dst)]>;
79 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
80 "stey\t{$src, $dst}",
81 [(store FP32:$src, rriaddr:$dst)]>;
82 def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
83 "std\t{$src, $dst}",
84 [(store FP64:$src, rriaddr12:$dst)]>;
85 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
86 "stdy\t{$src, $dst}",
87 [(store FP64:$src, rriaddr:$dst)]>;
89 def FCOPYSIGN32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
90 "cpsdr\t{$dst, $src2, $src1}",
91 [(set FP32:$dst, (fcopysign FP32:$src1, FP32:$src2))]>;
92 def FCOPYSIGN64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
93 "cpsdr\t{$dst, $src2, $src1}",
94 [(set FP64:$dst, (fcopysign FP64:$src1, FP64:$src2))]>;
101 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
102 "lcebr\t{$dst, $src}",
103 [(set FP32:$dst, (fneg FP32:$src)),
105 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
106 "lcdbr\t{$dst, $src}",
107 [(set FP64:$dst, (fneg FP64:$src)),
110 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
111 "lpebr\t{$dst, $src}",
112 [(set FP32:$dst, (fabs FP32:$src)),
114 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
115 "lpdbr\t{$dst, $src}",
116 [(set FP64:$dst, (fabs FP64:$src)),
119 def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
120 "lnebr\t{$dst, $src}",
121 [(set FP32:$dst, (fneg(fabs FP32:$src))),
123 def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
124 "lndbr\t{$dst, $src}",
125 [(set FP64:$dst, (fneg(fabs FP64:$src))),
129 let Constraints = "$src1 = $dst" in {
132 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
133 "aebr\t{$dst, $src2}",
134 [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
136 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
137 "adbr\t{$dst, $src2}",
138 [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
142 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
143 "aeb\t{$dst, $src2}",
144 [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr12:$src2))),
146 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
147 "adb\t{$dst, $src2}",
148 [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr12:$src2))),
151 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
152 "sebr\t{$dst, $src2}",
153 [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
155 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
156 "sdbr\t{$dst, $src2}",
157 [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
160 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
161 "seb\t{$dst, $src2}",
162 [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr12:$src2))),
164 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
165 "sdb\t{$dst, $src2}",
166 [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr12:$src2))),
171 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
172 "meebr\t{$dst, $src2}",
173 [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
174 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
175 "mdbr\t{$dst, $src2}",
176 [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
179 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
180 "meeb\t{$dst, $src2}",
181 [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr12:$src2)))]>;
182 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
183 "mdb\t{$dst, $src2}",
184 [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr12:$src2)))]>;
186 def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
187 "maebr\t{$dst, $src3, $src2}",
188 [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
190 def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
191 "maeb\t{$dst, $src3, $src2}",
192 [(set FP32:$dst, (fadd (fmul (load rriaddr12:$src2),
196 def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
197 "madbr\t{$dst, $src3, $src2}",
198 [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
200 def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
201 "madb\t{$dst, $src3, $src2}",
202 [(set FP64:$dst, (fadd (fmul (load rriaddr12:$src2),
206 def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
207 "msebr\t{$dst, $src3, $src2}",
208 [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
210 def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
211 "mseb\t{$dst, $src3, $src2}",
212 [(set FP32:$dst, (fsub (fmul (load rriaddr12:$src2),
216 def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
217 "msdbr\t{$dst, $src3, $src2}",
218 [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
220 def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
221 "msdb\t{$dst, $src3, $src2}",
222 [(set FP64:$dst, (fsub (fmul (load rriaddr12:$src2),
226 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
227 "debr\t{$dst, $src2}",
228 [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
229 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
230 "ddbr\t{$dst, $src2}",
231 [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
233 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
234 "deb\t{$dst, $src2}",
235 [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr12:$src2)))]>;
236 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
237 "ddb\t{$dst, $src2}",
238 [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr12:$src2)))]>;
240 } // Constraints = "$src1 = $dst"
242 def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
243 "sqebr\t{$dst, $src}",
244 [(set FP32:$dst, (fsqrt FP32:$src))]>;
245 def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
246 "sqdbr\t{$dst, $src}",
247 [(set FP64:$dst, (fsqrt FP64:$src))]>;
249 def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
250 "sqeb\t{$dst, $src}",
251 [(set FP32:$dst, (fsqrt (load rriaddr12:$src)))]>;
252 def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
253 "sqdb\t{$dst, $src}",
254 [(set FP64:$dst, (fsqrt (load rriaddr12:$src)))]>;
256 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
257 "ledbr\t{$dst, $src}",
258 [(set FP32:$dst, (fround FP64:$src))]>;
260 def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
261 "ldebr\t{$dst, $src}",
262 [(set FP64:$dst, (fextend FP32:$src))]>;
263 def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
264 "ldeb\t{$dst, $src}",
265 [(set FP64:$dst, (fextend (load rriaddr12:$src)))]>;
268 def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
269 "cefbr\t{$dst, $src}",
270 [(set FP32:$dst, (sint_to_fp GR32:$src)),
272 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
273 "cegbr\t{$dst, $src}",
274 [(set FP32:$dst, (sint_to_fp GR64:$src)),
277 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
278 "cdfbr\t{$dst, $src}",
279 [(set FP64:$dst, (sint_to_fp GR32:$src)),
281 def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
282 "cdgbr\t{$dst, $src}",
283 [(set FP64:$dst, (sint_to_fp GR64:$src)),
286 def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
287 "cfebr\t{$dst, 5, $src}",
288 [(set GR32:$dst, (fp_to_sint FP32:$src)),
290 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
291 "cfdbr\t{$dst, 5, $src}",
292 [(set GR32:$dst, (fp_to_sint FP64:$src)),
295 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
296 "cgebr\t{$dst, 5, $src}",
297 [(set GR64:$dst, (fp_to_sint FP32:$src)),
299 def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
300 "cgdbr\t{$dst, 5, $src}",
301 [(set GR64:$dst, (fp_to_sint FP64:$src)),
305 def FBCONVG64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
306 "lgdr\t{$dst, $src}",
307 [(set GR64:$dst, (bitconvert FP64:$src))]>;
308 def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
309 "ldgr\t{$dst, $src}",
310 [(set FP64:$dst, (bitconvert GR64:$src))]>;