Lines Matching refs:dst
79 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
81 [(set GR32:$dst,
83 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
85 [(set GR64:$dst,
101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
104 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
109 "jo\t$dst",
110 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O, PSW)]>;
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
112 "jh\t$dst",
113 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H, PSW)]>;
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
115 "jnle\t$dst",
116 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE, PSW)]>;
117 def JL : Pseudo<(outs), (ins brtarget:$dst),
118 "jl\t$dst",
119 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L, PSW)]>;
120 def JNHE: Pseudo<(outs), (ins brtarget:$dst),
121 "jnhe\t$dst",
122 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE, PSW)]>;
123 def JLH : Pseudo<(outs), (ins brtarget:$dst),
124 "jlh\t$dst",
125 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH, PSW)]>;
126 def JNE : Pseudo<(outs), (ins brtarget:$dst),
127 "jne\t$dst",
128 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE, PSW)]>;
129 def JE : Pseudo<(outs), (ins brtarget:$dst),
130 "je\t$dst",
131 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E, PSW)]>;
132 def JNLH: Pseudo<(outs), (ins brtarget:$dst),
133 "jnlh\t$dst",
134 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH, PSW)]>;
135 def JHE : Pseudo<(outs), (ins brtarget:$dst),
136 "jhe\t$dst",
137 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE, PSW)]>;
138 def JNL : Pseudo<(outs), (ins brtarget:$dst),
139 "jnl\t$dst",
140 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL, PSW)]>;
141 def JLE : Pseudo<(outs), (ins brtarget:$dst),
142 "jle\t$dst",
143 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE, PSW)]>;
144 def JNH : Pseudo<(outs), (ins brtarget:$dst),
145 "jnh\t$dst",
146 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH, PSW)]>;
147 def JNO : Pseudo<(outs), (ins brtarget:$dst),
148 "jno\t$dst",
149 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO, PSW)]>;
162 def CALLi : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
163 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
164 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
165 "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
176 (outs GR64:$dst), (ins laaddr:$src),
177 "lay\t{$dst, $src}",
178 [(set GR64:$dst, laaddr:$src)]>;
180 (outs GR64:$dst), (ins i64imm:$src),
181 "larl\t{$dst, $src}",
182 [(set GR64:$dst,
193 (outs GR32:$dst), (ins GR32:$src),
194 "lr\t{$dst, $src}",
197 (outs GR64:$dst), (ins GR64:$src),
198 "lgr\t{$dst, $src}",
200 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
202 "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
203 "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
205 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
207 "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
208 "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
213 (outs GR64:$dst), (ins GR32:$src),
214 "lgfr\t{$dst, $src}",
215 [(set GR64:$dst, (sext GR32:$src))]>;
217 (outs GR64:$dst), (ins GR32:$src),
218 "llgfr\t{$dst, $src}",
219 [(set GR64:$dst, (zext GR32:$src))]>;
223 (outs GR32:$dst), (ins s16imm:$src),
224 "lhi\t{$dst, $src}",
225 [(set GR32:$dst, immSExt16:$src)]>;
227 (outs GR64:$dst), (ins s16imm64:$src),
228 "lghi\t{$dst, $src}",
229 [(set GR64:$dst, immSExt16:$src)]>;
232 (outs GR64:$dst), (ins u16imm:$src),
233 "llill\t{$dst, $src}",
234 [(set GR64:$dst, i64ll16:$src)]>;
236 (outs GR64:$dst), (ins u16imm:$src),
237 "llilh\t{$dst, $src}",
238 [(set GR64:$dst, i64lh16:$src)]>;
240 (outs GR64:$dst), (ins u16imm:$src),
241 "llihl\t{$dst, $src}",
242 [(set GR64:$dst, i64hl16:$src)]>;
244 (outs GR64:$dst), (ins u16imm:$src),
245 "llihh\t{$dst, $src}",
246 [(set GR64:$dst, i64hh16:$src)]>;
249 (outs GR64:$dst), (ins s32imm64:$src),
250 "lgfi\t{$dst, $src}",
251 [(set GR64:$dst, immSExt32:$src)]>;
253 (outs GR64:$dst), (ins u32imm:$src),
254 "llilf\t{$dst, $src}",
255 [(set GR64:$dst, i64lo32:$src)]>;
256 def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins u32imm:$src),
257 "llihf\t{$dst, $src}",
258 [(set GR64:$dst, i64hi32:$src)]>;
263 (outs GR32:$dst), (ins rriaddr12:$src),
264 "l\t{$dst, $src}",
265 [(set GR32:$dst, (load rriaddr12:$src))]>;
267 (outs GR32:$dst), (ins rriaddr:$src),
268 "ly\t{$dst, $src}",
269 [(set GR32:$dst, (load rriaddr:$src))]>;
271 (outs GR64:$dst), (ins rriaddr:$src),
272 "lg\t{$dst, $src}",
273 [(set GR64:$dst, (load rriaddr:$src))]>;
274 def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src),
276 "\tl\t${dst:subreg_odd}, $src\n"
277 "\tl\t${dst:subreg_even}, 4+$src",
278 [(set GR64P:$dst, (load rriaddr12:$src))]>;
279 def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src),
281 "\tly\t${dst:subreg_odd}, $src\n"
282 "\tly\t${dst:subreg_even}, 4+$src",
283 [(set GR64P:$dst, (load rriaddr:$src))]>;
284 def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src),
286 "\tlg\t${dst:subreg_odd}, $src\n"
287 "\tlg\t${dst:subreg_even}, 8+$src",
288 [(set GR128:$dst, (load rriaddr:$src))]>;
292 (outs), (ins rriaddr12:$dst, GR32:$src),
293 "st\t{$src, $dst}",
294 [(store GR32:$src, rriaddr12:$dst)]>;
296 (outs), (ins rriaddr:$dst, GR32:$src),
297 "sty\t{$src, $dst}",
298 [(store GR32:$src, rriaddr:$dst)]>;
300 (outs), (ins rriaddr:$dst, GR64:$src),
301 "stg\t{$src, $dst}",
302 [(store GR64:$src, rriaddr:$dst)]>;
303 def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src),
305 "\tst\t${src:subreg_odd}, $dst\n"
306 "\tst\t${src:subreg_even}, 4+$dst",
307 [(store GR64P:$src, rriaddr12:$dst)]>;
308 def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src),
310 "\tsty\t${src:subreg_odd}, $dst\n"
311 "\tsty\t${src:subreg_even}, 4+$dst",
312 [(store GR64P:$src, rriaddr:$dst)]>;
313 def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src),
315 "\tstg\t${src:subreg_odd}, $dst\n"
316 "\tstg\t${src:subreg_even}, 8+$dst",
317 [(store GR128:$src, rriaddr:$dst)]>;
320 (outs), (ins riaddr12:$dst, i32i8imm:$src),
321 "mvi\t{$dst, $src}",
322 [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
324 (outs), (ins riaddr:$dst, i32i8imm:$src),
325 "mviy\t{$dst, $src}",
326 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
330 (outs), (ins riaddr12:$dst, s16imm:$src),
331 "mvhhi\t{$dst, $src}",
332 [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
335 (outs), (ins riaddr12:$dst, s32imm:$src),
336 "mvhi\t{$dst, $src}",
337 [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
340 (outs), (ins riaddr12:$dst, s32imm64:$src),
341 "mvghi\t{$dst, $src}",
342 [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
348 (outs GR32:$dst), (ins GR32:$src),
349 "lbr\t{$dst, $src}",
350 [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
352 (outs GR64:$dst), (ins GR64:$src),
353 "lgbr\t{$dst, $src}",
354 [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
356 (outs GR32:$dst), (ins GR32:$src),
357 "lhr\t{$dst, $src}",
358 [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
360 (outs GR64:$dst), (ins GR64:$src),
361 "lghr\t{$dst, $src}",
362 [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
366 (outs GR32:$dst), (ins rriaddr:$src),
367 "lb\t{$dst, $src}",
368 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
370 (outs GR32:$dst), (ins rriaddr12:$src),
371 "lh\t{$dst, $src}",
372 [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
374 (outs GR32:$dst), (ins rriaddr:$src),
375 "lhy\t{$dst, $src}",
376 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
378 (outs GR64:$dst), (ins rriaddr:$src),
379 "lgb\t{$dst, $src}",
380 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
382 (outs GR64:$dst), (ins rriaddr:$src),
383 "lgh\t{$dst, $src}",
384 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
386 (outs GR64:$dst), (ins rriaddr:$src),
387 "lgf\t{$dst, $src}",
388 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
391 (outs GR32:$dst), (ins rriaddr:$src),
392 "llc\t{$dst, $src}",
393 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
395 (outs GR32:$dst), (ins rriaddr:$src),
396 "llh\t{$dst, $src}",
397 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
399 (outs GR64:$dst), (ins rriaddr:$src),
400 "llgc\t{$dst, $src}",
401 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
403 (outs GR64:$dst), (ins rriaddr:$src),
404 "llgh\t{$dst, $src}",
405 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
407 (outs GR64:$dst), (ins rriaddr:$src),
408 "llgf\t{$dst, $src}",
409 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
413 (outs), (ins rriaddr12:$dst, GR32:$src),
414 "stc\t{$src, $dst}",
415 [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
418 (outs), (ins rriaddr:$dst, GR32:$src),
419 "stcy\t{$src, $dst}",
420 [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
423 (outs), (ins rriaddr12:$dst, GR32:$src),
424 "sth\t{$src, $dst}",
425 [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
428 (outs), (ins rriaddr:$dst, GR32:$src),
429 "sthy\t{$src, $dst}",
430 [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
433 (outs), (ins rriaddr12:$dst, GR64:$src),
434 "stc\t{$src, $dst}",
435 [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
438 (outs), (ins rriaddr:$dst, GR64:$src),
439 "stcy\t{$src, $dst}",
440 [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
443 (outs), (ins rriaddr12:$dst, GR64:$src),
444 "sth\t{$src, $dst}",
445 [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
448 (outs), (ins rriaddr:$dst, GR64:$src),
449 "sthy\t{$src, $dst}",
450 [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
453 (outs), (ins rriaddr12:$dst, GR64:$src),
454 "st\t{$src, $dst}",
455 [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
458 (outs), (ins rriaddr:$dst, GR64:$src),
459 "sty\t{$src, $dst}",
460 [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
465 (outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
466 "stmy\t{$from, $to, $dst}",
469 (outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
470 "stmg\t{$from, $to, $dst}",
473 (outs GR32:$from, GR32:$to), (ins riaddr:$dst),
474 "lmy\t{$from, $to, $dst}",
477 (outs GR64:$from, GR64:$to), (ins riaddr:$dst),
478 "lmg\t{$from, $to, $dst}",
482 Constraints = "$src = $dst" in {
483 def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
484 "lhi\t${dst:subreg_even}, 0",
486 def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
487 "lghi\t${dst:subreg_even}, 0",
493 (outs GR32:$dst), (ins GR32:$src),
494 "lrvr\t{$dst, $src}",
495 [(set GR32:$dst, (bswap GR32:$src))]>;
497 (outs GR64:$dst), (ins GR64:$src),
498 "lrvgr\t{$dst, $src}",
499 [(set GR64:$dst, (bswap GR64:$src))]>;
502 //def BSWAP16rm : RXYI<0x1FE3, (outs GR32:$dst), (ins rriaddr:$src),
503 // "lrvh\t{$dst, $src}",
504 // [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>;
505 def BSWAP32rm : RXYI<0x1EE3, (outs GR32:$dst), (ins rriaddr:$src),
506 "lrv\t{$dst, $src}",
507 [(set GR32:$dst, (bswap (load rriaddr:$src)))]>;
508 def BSWAP64rm : RXYI<0x0FE3, (outs GR64:$dst), (ins rriaddr:$src),
509 "lrvg\t{$dst, $src}",
510 [(set GR64:$dst, (bswap (load rriaddr:$src)))]>;
512 //def BSWAP16mr : RXYI<0xE33F, (outs), (ins rriaddr:$dst, GR32:$src),
513 // "strvh\t{$src, $dst}",
514 // [(truncstorei16 (bswap GR32:$src), rriaddr:$dst)]>;
515 def BSWAP32mr : RXYI<0xE33E, (outs), (ins rriaddr:$dst, GR32:$src),
516 "strv\t{$src, $dst}",
517 [(store (bswap GR32:$src), rriaddr:$dst)]>;
518 def BSWAP64mr : RXYI<0xE32F, (outs), (ins rriaddr:$dst, GR64:$src),
519 "strvg\t{$src, $dst}",
520 [(store (bswap GR64:$src), rriaddr:$dst)]>;
527 (outs GR32:$dst), (ins GR32:$src),
528 "lcr\t{$dst, $src}",
529 [(set GR32:$dst, (ineg GR32:$src)),
531 def NEG64rr : RREI<0xB903, (outs GR64:$dst), (ins GR64:$src),
532 "lcgr\t{$dst, $src}",
533 [(set GR64:$dst, (ineg GR64:$src)),
535 def NEG64rr32 : RREI<0xB913, (outs GR64:$dst), (ins GR32:$src),
536 "lcgfr\t{$dst, $src}",
537 [(set GR64:$dst, (ineg (sext GR32:$src))),
541 let Constraints = "$src1 = $dst" in {
546 def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
547 "ar\t{$dst, $src2}",
548 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
550 def ADD64rr : RREI<0xB908, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
551 "agr\t{$dst, $src2}",
552 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
556 def ADD32rm : RXI<0x5A, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
557 "a\t{$dst, $src2}",
558 [(set GR32:$dst, (add GR32:$src1, (load rriaddr12:$src2))),
560 def ADD32rmy : RXYI<0xE35A, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
561 "ay\t{$dst, $src2}",
562 [(set GR32:$dst, (add GR32:$src1, (load rriaddr:$src2))),
564 def ADD64rm : RXYI<0xE308, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
565 "ag\t{$dst, $src2}",
566 [(set GR64:$dst, (add GR64:$src1, (load rriaddr:$src2))),
571 (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
572 "ahi\t{$dst, $src2}",
573 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
576 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
577 "afi\t{$dst, $src2}",
578 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
581 (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
582 "aghi\t{$dst, $src2}",
583 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
586 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
587 "agfi\t{$dst, $src2}",
588 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
592 def ADC32rr : RRI<0x1E, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
593 "alr\t{$dst, $src2}",
594 [(set GR32:$dst, (addc GR32:$src1, GR32:$src2))]>;
595 def ADC64rr : RREI<0xB90A, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
596 "algr\t{$dst, $src2}",
597 [(set GR64:$dst, (addc GR64:$src1, GR64:$src2))]>;
601 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
602 "alfi\t{$dst, $src2}",
603 [(set GR32:$dst, (addc GR32:$src1, imm:$src2))]>;
605 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
606 "algfi\t{$dst, $src2}",
607 [(set GR64:$dst, (addc GR64:$src1, immSExt32:$src2))]>;
610 def ADDE32rr : RREI<0xB998, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
611 "alcr\t{$dst, $src2}",
612 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2)),
614 def ADDE64rr : RREI<0xB988, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
615 "alcgr\t{$dst, $src2}",
616 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2)),
622 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
623 "nr\t{$dst, $src2}",
624 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
626 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
627 "ngr\t{$dst, $src2}",
628 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
631 def AND32rm : RXI<0x54, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
632 "n\t{$dst, $src2}",
633 [(set GR32:$dst, (and GR32:$src1, (load rriaddr12:$src2))),
635 def AND32rmy : RXYI<0xE354, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
636 "ny\t{$dst, $src2}",
637 [(set GR32:$dst, (and GR32:$src1, (load rriaddr:$src2))),
639 def AND64rm : RXYI<0xE360, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
640 "ng\t{$dst, $src2}",
641 [(set GR64:$dst, (and GR64:$src1, (load rriaddr:$src2))),
645 (outs GR32:$dst), (ins GR32:$src1, u16imm:$src2),
646 "nill\t{$dst, $src2}",
647 [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
649 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
650 "nill\t{$dst, $src2}",
651 [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
654 (outs GR32:$dst), (ins GR32:$src1, u16imm:$src2),
655 "nilh\t{$dst, $src2}",
656 [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
658 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
659 "nilh\t{$dst, $src2}",
660 [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
663 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
664 "nihl\t{$dst, $src2}",
665 [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
667 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
668 "nihh\t{$dst, $src2}",
669 [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
672 (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2),
673 "nilf\t{$dst, $src2}",
674 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
676 (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2),
677 "nilf\t{$dst, $src2}",
678 [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
680 (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2),
681 "nihf\t{$dst, $src2}",
682 [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
686 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
687 "or\t{$dst, $src2}",
688 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
690 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
691 "ogr\t{$dst, $src2}",
692 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
695 def OR32rm : RXI<0x56, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
696 "o\t{$dst, $src2}",
697 [(set GR32:$dst, (or GR32:$src1, (load rriaddr12:$src2))),
699 def OR32rmy : RXYI<0xE356, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
700 "oy\t{$dst, $src2}",
701 [(set GR32:$dst, (or GR32:$src1, (load rriaddr:$src2))),
703 def OR64rm : RXYI<0xE381, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
704 "og\t{$dst, $src2}",
705 [(set GR64:$dst, (or GR64:$src1, (load rriaddr:$src2))),
710 (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2),
711 "oill\t{$dst, $src2}",
712 [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
714 (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2),
715 "oilh\t{$dst, $src2}",
716 [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
718 (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2),
719 "oilf\t{$dst, $src2}",
720 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
723 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
724 "oill\t{$dst, $src2}",
725 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
727 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
728 "oilh\t{$dst, $src2}",
729 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
731 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
732 "oihl\t{$dst, $src2}",
733 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
735 (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2),
736 "oihh\t{$dst, $src2}",
737 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
740 (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2),
741 "oilf\t{$dst, $src2}",
742 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
744 (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2),
745 "oihf\t{$dst, $src2}",
746 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
749 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
750 "sr\t{$dst, $src2}",
751 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
753 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
754 "sgr\t{$dst, $src2}",
755 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
757 def SUB32rm : RXI<0x5B, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
758 "s\t{$dst, $src2}",
759 [(set GR32:$dst, (sub GR32:$src1, (load rriaddr12:$src2))),
761 def SUB32rmy : RXYI<0xE35B, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
762 "sy\t{$dst, $src2}",
763 [(set GR32:$dst, (sub GR32:$src1, (load rriaddr:$src2))),
765 def SUB64rm : RXYI<0xE309, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
766 "sg\t{$dst, $src2}",
767 [(set GR64:$dst, (sub GR64:$src1, (load rriaddr:$src2))),
771 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
772 "slr\t{$dst, $src2}",
773 [(set GR32:$dst, (subc GR32:$src1, GR32:$src2))]>;
775 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
776 "slgr\t{$dst, $src2}",
777 [(set GR64:$dst, (subc GR64:$src1, GR64:$src2))]>;
780 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
781 "sllfi\t{$dst, $src2}",
782 [(set GR32:$dst, (subc GR32:$src1, imm:$src2))]>;
784 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
785 "slgfi\t{$dst, $src2}",
786 [(set GR64:$dst, (subc GR64:$src1, immSExt32:$src2))]>;
789 def SUBE32rr : RREI<0xB999, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
790 "slbr\t{$dst, $src2}",
791 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2)),
793 def SUBE64rr : RREI<0xB989, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
794 "slbgr\t{$dst, $src2}",
795 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2)),
801 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
802 "xr\t{$dst, $src2}",
803 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
805 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
806 "xgr\t{$dst, $src2}",
807 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
810 def XOR32rm : RXI<0x57,(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
811 "x\t{$dst, $src2}",
812 [(set GR32:$dst, (xor GR32:$src1, (load rriaddr12:$src2))),
814 def XOR32rmy : RXYI<0xE357, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
815 "xy\t{$dst, $src2}",
816 [(set GR32:$dst, (xor GR32:$src1, (load rriaddr:$src2))),
818 def XOR64rm : RXYI<0xE382, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
819 "xg\t{$dst, $src2}",
820 [(set GR64:$dst, (xor GR64:$src1, (load rriaddr:$src2))),
824 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
825 "xilf\t{$dst, $src2}",
826 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
832 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
833 "msr\t{$dst, $src2}",
834 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
836 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
837 "msgr\t{$dst, $src2}",
838 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
842 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
843 "mr\t{$dst, $src2}",
846 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
847 "mlr\t{$dst, $src2}",
850 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
851 "mlgr\t{$dst, $src2}",
855 (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
856 "mhi\t{$dst, $src2}",
857 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
859 (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
860 "mghi\t{$dst, $src2}",
861 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
865 (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
866 "msfi\t{$dst, $src2}",
867 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
870 (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
871 "msgfi\t{$dst, $src2}",
872 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
877 (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
878 "ms\t{$dst, $src2}",
879 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
881 (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
882 "msy\t{$dst, $src2}",
883 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
885 (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
886 "msg\t{$dst, $src2}",
887 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
890 (outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
891 "msgfr\t{$dst, $src2}",
892 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
895 (outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
896 "dsgfr\t{$dst, $src2}",
899 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
900 "dsgr\t{$dst, $src2}",
904 (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
905 "dlr\t{$dst, $src2}",
908 (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
909 "dlgr\t{$dst, $src2}",
913 (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
914 "dsgf\t{$dst, $src2}",
917 (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
918 "dsg\t{$dst, $src2}",
921 def UDIVREM32m : RXYI<0xE397, (outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
922 "dl\t{$dst, $src2}",
924 def UDIVREM64m : RXYI<0xE387, (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
925 "dlg\t{$dst, $src2}",
928 } // Constraints = "$src1 = $dst"
933 let Constraints = "$src = $dst" in
935 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
937 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
939 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
940 "srlg\t{$dst, $src, $amt}",
941 [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
943 let Constraints = "$src = $dst" in
945 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
947 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
949 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
950 "sllg\t{$dst, $src, $amt}",
951 [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
954 let Constraints = "$src = $dst" in
956 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
958 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
962 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
963 "srag\t{$dst, $src, $amt}",
964 [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
969 (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
970 "rll\t{$dst, $src, $amt}",
971 [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
973 (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
974 "rllg\t{$dst, $src, $amt}",
975 [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
1077 (outs GR128:$dst), (ins GR64:$src),
1078 "flogr\t{$dst, $src}",
1095 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
1096 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;