Lines Matching refs:v2f64
823 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); in X86TargetLowering()
842 setOperationAction(ISD::FADD, MVT::v2f64, Legal); in X86TargetLowering()
843 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); in X86TargetLowering()
844 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); in X86TargetLowering()
845 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in X86TargetLowering()
846 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in X86TargetLowering()
847 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); in X86TargetLowering()
849 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); in X86TargetLowering()
860 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); in X86TargetLowering()
883 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in X86TargetLowering()
885 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in X86TargetLowering()
887 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in X86TargetLowering()
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); in X86TargetLowering()
919 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); in X86TargetLowering()
921 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); in X86TargetLowering()
1292 case MVT::v4f32: case MVT::v2f64: in findRepresentativeClass()
3043 if (VT == MVT::v2f64 || VT == MVT::v2i64) in isPSHUFDMask()
5214 case MVT::v4f32: NewVT = MVT::v2f64; break; in RewriteAsNarrowerShuffle()
5249 if (VT == MVT::v2f64 || VT == MVT::v4f32) { in getVZextMovL()
5256 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; in getVZextMovL()
5262 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; in getVZextMovL()
5537 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); in getMOVDDup()
5539 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, in getMOVDDup()
5552 if (HasSSE2 && VT == MVT::v2f64) in getMOVLowToHigh()
5638 case MVT::v2f64: in getUNPCKLOpcode()
5655 case MVT::v2f64: return X86ISD::UNPCKHPD; in getUNPCKHOpcode()
5768 if (VT != MVT::v2i64 && VT != MVT::v2f64) in LowerVECTOR_SHUFFLE()
5771 if (VT != MVT::v2i64 && VT != MVT::v2f64) in LowerVECTOR_SHUFFLE()
5783 (VT == MVT::v2f64 || VT == MVT::v2i64)) in LowerVECTOR_SHUFFLE()
5798 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) in LowerVECTOR_SHUFFLE()
5827 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) in LowerVECTOR_SHUFFLE()
5942 if (VT == MVT::v2f64) { in LowerVECTOR_SHUFFLE()
5966 if (VT == MVT::v2f64 || VT == MVT::v2i64) in LowerVECTOR_SHUFFLE()
5972 if (VT != MVT::v2i64 && VT != MVT::v2f64) in LowerVECTOR_SHUFFLE()
5976 if (VT != MVT::v2i64 && VT != MVT::v2f64) in LowerVECTOR_SHUFFLE()
6900 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); in LowerUINT_TO_FP_i64()
6901 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, in LowerUINT_TO_FP_i64()
6904 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); in LowerUINT_TO_FP_i64()
6908 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, in LowerUINT_TO_FP_i64()
6909 DAG.getUNDEF(MVT::v2f64), ShufMask); in LowerUINT_TO_FP_i64()
6910 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); in LowerUINT_TO_FP_i64()
6930 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), in LowerUINT_TO_FP_i32()
6937 MVT::v2f64, Load)), in LowerUINT_TO_FP_i32()
6940 MVT::v2f64, Bias))); in LowerUINT_TO_FP_i32()
6942 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), in LowerUINT_TO_FP_i32()
7253 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); in LowerFCOPYSIGN()
7254 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, in LowerFCOPYSIGN()
7579 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); in LowerVSETCC()
13031 case MVT::v2f64: in getRegForInlineAsmConstraint()