Lines Matching refs:dst
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
150 let Constraints = "$src1 = $dst" in {
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
228 addr:$dst),
229 (MOVSSmr addr:$dst,
232 addr:$dst),
233 (MOVSDmr addr:$dst,
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
346 [(set RC:$dst,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
367 "\t{$src2, $dst|$dst, $src2}">;
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
387 (iPTR 0))), addr:$dst)]>;
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
412 (iPTR 0))), addr:$dst)]>;
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
418 [(set VR128:$dst,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
424 [(set VR128:$dst,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
432 [(set VR128:$dst,
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
437 [(set VR128:$dst,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
536 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
538 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
540 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
542 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
544 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
546 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
548 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
550 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
558 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
559 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
560 [(set DstRC:$dst, (Int SrcRC:$src))]>;
561 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
562 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
563 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
569 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
571 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
572 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
573 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
574 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
577 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
578 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
579 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
598 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
600 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
622 let Constraints = "$src1 = $dst" in {
663 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
665 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
668 "cvtdq2ps\t{$src, $dst|$dst, $src}",
671 "cvtdq2ps\t{$src, $dst|$dst, $src}",
676 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
678 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
680 "cvtdq2ps\t{$src, $dst|$dst, $src}",
687 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
689 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
691 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
693 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
699 "cvtsd2ss\t{$src, $dst|$dst, $src}",
700 [(set FR32:$dst, (fround FR64:$src))]>;
701 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
702 "cvtsd2ss\t{$src, $dst|$dst, $src}",
703 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
709 let Constraints = "$src1 = $dst" in
715 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
721 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
733 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
734 "cvtss2sd\t{$src, $dst|$dst, $src}",
735 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
737 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
738 "cvtss2sd\t{$src, $dst|$dst, $src}",
739 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
743 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
744 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
745 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
749 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
750 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
751 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
754 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
756 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
757 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
758 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
762 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
763 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
764 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
775 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
776 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
777 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
779 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
780 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
781 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
784 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
785 "cvtdq2ps\t{$src, $dst|$dst, $src}",
786 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
788 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
789 "cvtdq2ps\t{$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
796 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
797 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
798 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
800 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
801 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
805 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
806 "cvtdq2pd\t{$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
809 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
810 "cvtdq2pd\t{$src, $dst|$dst, $src}",
811 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
817 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
818 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
819 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
820 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
821 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
822 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
823 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
824 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
825 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
826 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
828 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
830 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtps2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
834 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
836 "cvtps2dq\t{$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
839 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
840 "cvtps2dq\t{$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
842 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
843 "cvtps2dq\t{$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
848 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
849 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
850 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
852 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
853 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
854 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
857 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
858 "cvtpd2dq\t{$src, $dst|$dst, $src}",
859 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
861 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
862 "cvtpd2dq\t{$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
870 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
871 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
872 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
873 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
874 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
875 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
876 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
877 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
878 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
879 "cvttps2dq\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst,
882 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
883 "cvttps2dq\t{$src, $dst|$dst, $src}",
884 [(set VR128:$dst,
888 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
889 "vcvttps2dq\t{$src, $dst|$dst, $src}",
890 [(set VR128:$dst,
893 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
894 "vcvttps2dq\t{$src, $dst|$dst, $src}",
895 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
899 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
901 "cvttpd2dq\t{$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
904 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
906 "cvttpd2dq\t{$src, $dst|$dst, $src}",
907 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
909 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
910 "cvttpd2dq\t{$src, $dst|$dst, $src}",
911 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
912 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
913 "cvttpd2dq\t{$src, $dst|$dst, $src}",
914 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
920 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
921 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
922 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
923 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
926 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
927 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
928 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
929 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
932 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
933 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
934 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
935 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
940 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
941 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
942 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
943 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
944 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
945 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
946 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
947 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
949 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
950 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
951 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
952 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
954 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
955 "vcvtps2pd\t{$src, $dst|$dst, $src}",
956 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
958 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
959 "vcvtps2pd\t{$src, $dst|$dst, $src}",
960 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
963 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
964 "cvtps2pd\t{$src, $dst|$dst, $src}",
965 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
967 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
968 "cvtps2pd\t{$src, $dst|$dst, $src}",
969 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
977 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
978 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
979 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
980 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
983 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
984 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
985 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
986 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
989 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
990 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
991 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
992 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
993 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
994 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
995 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
996 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
999 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1000 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1001 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1002 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1004 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1007 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1008 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1009 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1010 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1011 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1012 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1057 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1061 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1067 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1071 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1077 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1078 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1081 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1082 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1086 let Constraints = "$src1 = $dst" in {
1088 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1089 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1090 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1092 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1093 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1094 … [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1096 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1097 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1098 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1100 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1101 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1102 … [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1104 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1106 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1107 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1109 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1110 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1112 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1113 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1115 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1116 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1121 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1123 [(set VR128:$dst, (Int VR128:$src1,
1125 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1127 [(set VR128:$dst, (Int VR128:$src1,
1133 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1136 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1138 let Constraints = "$src1 = $dst" in {
1140 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1142 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1209 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1210 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1212 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1213 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1218 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1221 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1226 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1227 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1230 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1231 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1234 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1235 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1238 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1239 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1241 let Constraints = "$src1 = $dst" in {
1243 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1244 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1247 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1248 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1269 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1271 [(set RC:$dst, (vt (shufp:$src3
1274 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1276 [(set RC:$dst,
1281 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1284 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1287 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1290 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1293 let Constraints = "$src1 = $dst" in {
1295 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1299 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1313 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1314 asm, [(set RC:$dst,
1317 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1318 asm, [(set RC:$dst,
1325 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1328 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1331 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1334 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1338 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1341 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1344 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1347 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1350 let Constraints = "$src1 = $dst" in {
1352 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1355 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1358 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1361 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1363 } // Constraints = "$src1 = $dst"
1373 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1374 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1375 [(set GR32:$dst, (Int RC:$src))], d>;
1376 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1377 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1397 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1398 "movmskpd\t{$src, $dst|$dst, $src}",
1399 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1400 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1401 "movmskpd\t{$src, $dst|$dst, $src}",
1402 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1403 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1404 "movmskps\t{$src, $dst|$dst, $src}",
1405 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1406 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1407 "movmskps\t{$src, $dst|$dst, $src}",
1408 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1411 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1412 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1413 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1414 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1416 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1417 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1418 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1419 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1433 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1434 [(set FR32:$dst, fp32imm0)]>,
1436 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1437 [(set FR64:$dst, fpimm0)]>,
1439 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1440 [(set FR32:$dst, fp32imm0)]>,
1442 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1443 [(set FR64:$dst, fpimm0)]>,
1450 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1451 "movaps\t{$src, $dst|$dst, $src}", []>;
1452 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1453 "movapd\t{$src, $dst|$dst, $src}", []>;
1459 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1460 "movaps\t{$src, $dst|$dst, $src}",
1461 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1462 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1463 "movapd\t{$src, $dst|$dst, $src}",
1464 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1481 let Constraints = "$src1 = $dst" in {
1507 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1508 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1513 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1515 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1519 let Constraints = "$src1 = $dst" in {
1522 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1523 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1528 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1530 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1541 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1542 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1547 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1549 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1673 let Constraints = "$src1 = $dst" in {
1710 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1711 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1712 [(set FR32:$dst, (OpNode FR32:$src))]>;
1717 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1718 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1719 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1721 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1722 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1723 [(set VR128:$dst, (F32Int VR128:$src))]>;
1724 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1725 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1726 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1732 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1734 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1735 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1737 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1739 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1741 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1742 [(set VR128:$dst, (F32Int VR128:$src))]>;
1743 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1745 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1746 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1751 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1752 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1753 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1754 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1755 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1756 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1761 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1762 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1763 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1764 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1765 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1766 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1772 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1773 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1774 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1775 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1776 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1777 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1783 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1784 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1785 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1786 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1787 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1788 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1794 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1795 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1796 [(set FR64:$dst, (OpNode FR64:$src))]>;
1798 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1799 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1800 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1802 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1803 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1804 [(set VR128:$dst, (F64Int VR128:$src))]>;
1805 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1806 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1807 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1813 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1815 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1816 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1819 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1820 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1821 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1822 [(set VR128:$dst, (F64Int VR128:$src))]>;
1823 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1824 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1825 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1831 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1832 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1833 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1834 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1835 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1836 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1841 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1842 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1843 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1844 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1845 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1846 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1852 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1853 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1854 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1855 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1856 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1857 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1863 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1864 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1865 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1866 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1867 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1868 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1940 (ins f128mem:$dst, VR128:$src),
1941 "movntps\t{$src, $dst|$dst, $src}",
1943 addr:$dst)]>, VEX;
1945 (ins f128mem:$dst, VR128:$src),
1946 "movntpd\t{$src, $dst|$dst, $src}",
1948 addr:$dst)]>, VEX;
1950 (ins f128mem:$dst, VR128:$src),
1951 "movntdq\t{$src, $dst|$dst, $src}",
1953 addr:$dst)]>, VEX;
1957 (ins f128mem:$dst, VR128:$src),
1958 "movntdq\t{$src, $dst|$dst, $src}",
1960 addr:$dst)]>, VEX;
1962 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1963 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
1966 (ins f256mem:$dst, VR256:$src),
1967 "movntps\t{$src, $dst|$dst, $src}",
1969 addr:$dst)]>, VEX;
1971 (ins f256mem:$dst, VR256:$src),
1972 "movntpd\t{$src, $dst|$dst, $src}",
1974 addr:$dst)]>, VEX;
1976 (ins f256mem:$dst, VR256:$src),
1977 "movntdq\t{$src, $dst|$dst, $src}",
1979 addr:$dst)]>, VEX;
1982 (ins f256mem:$dst, VR256:$src),
1983 "movntdq\t{$src, $dst|$dst, $src}",
1985 addr:$dst)]>, VEX;
1988 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1989 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1990 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
1991 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
1992 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
1993 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
1996 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1997 "movntps\t{$src, $dst|$dst, $src}",
1998 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1999 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2000 "movntpd\t{$src, $dst|$dst, $src}",
2001 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2003 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2004 "movntdq\t{$src, $dst|$dst, $src}",
2005 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2008 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2009 "movntdq\t{$src, $dst|$dst, $src}",
2010 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2012 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2013 (MOVNTDQmr addr:$dst, VR128:$src)>;
2016 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2017 "movnti{l}\t{$src, $dst|$dst, $src}",
2018 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2020 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2021 "movnti{q}\t{$src, $dst|$dst, $src}",
2022 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2053 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2054 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2055 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2056 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2058 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2059 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2072 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2073 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2074 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2075 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2076 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2077 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2078 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2079 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2081 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2082 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2098 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2099 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2103 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2104 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2113 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2114 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2115 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2116 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2118 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2119 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2120 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2121 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2124 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2125 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2126 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2127 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2129 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2130 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2131 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2132 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2138 (ins i128mem:$dst, VR128:$src),
2139 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2141 (ins i256mem:$dst, VR256:$src),
2142 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2144 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2145 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2146 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2147 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2152 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2153 "movdqa\t{$src, $dst|$dst, $src}", []>;
2155 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2156 "movdqu\t{$src, $dst|$dst, $src}",
2160 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2161 "movdqa\t{$src, $dst|$dst, $src}",
2162 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2163 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2164 "movdqu\t{$src, $dst|$dst, $src}",
2165 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2170 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2171 "movdqa\t{$src, $dst|$dst, $src}",
2172 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2173 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2174 "movdqu\t{$src, $dst|$dst, $src}",
2175 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2180 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2181 "vmovdqu\t{$src, $dst|$dst, $src}",
2182 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2185 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2186 "movdqu\t{$src, $dst|$dst, $src}",
2187 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2193 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2194 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2205 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2208 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2209 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2210 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2211 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2214 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2216 [(set VR128:$dst, (IntId VR128:$src1,
2223 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2226 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2227 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2228 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2229 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2234 [(set VR128:$dst, (IntId VR128:$src1,
2236 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2241 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2248 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2251 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2253 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2254 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2257 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2259 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2271 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2274 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2275 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2276 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2277 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2282 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2341 let Constraints = "$src1 = $dst" in {
2373 } // Constraints = "$src1 = $dst"
2415 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2416 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2419 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2420 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2425 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2426 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2427 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2431 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2432 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2433 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2439 let Constraints = "$src1 = $dst" in {
2467 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2468 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2470 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2471 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2475 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2476 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2479 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2480 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2482 } // Constraints = "$src1 = $dst"
2541 let Constraints = "$src1 = $dst" in {
2548 } // Constraints = "$src1 = $dst"
2589 let Constraints = "$src1 = $dst" in {
2593 } // Constraints = "$src1 = $dst"
2603 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2605 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2606 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2609 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2611 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2612 [(set VR128:$dst, (vt (pshuf_frag:$src2
2651 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2653 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2654 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2655 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2657 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2659 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2660 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2661 [(set VR128:$dst, (unp_frag VR128:$src1,
2677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2678 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2679 [(set VR128:$dst,
2682 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2683 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2684 [(set VR128:$dst,
2698 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2699 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 [(set VR128:$dst,
2703 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2704 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 [(set VR128:$dst,
2710 let Constraints = "$src1 = $dst" in {
2718 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2719 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2720 [(set VR128:$dst,
2723 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2724 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2725 [(set VR128:$dst,
2736 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2737 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2738 [(set VR128:$dst,
2741 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2742 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2743 [(set VR128:$dst,
2757 (outs VR128:$dst), (ins VR128:$src1,
2760 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2761 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2762 [(set VR128:$dst,
2765 (outs VR128:$dst), (ins VR128:$src1,
2768 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2769 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2770 [(set VR128:$dst,
2778 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2779 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2780 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2783 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2784 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2785 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2791 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2793 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2797 let Constraints = "$src1 = $dst" in
2808 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2809 "pmovmskb\t{$src, $dst|$dst, $src}",
2810 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2811 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2812 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2813 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2814 "pmovmskb\t{$src, $dst|$dst, $src}",
2815 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2852 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2853 "movd\t{$src, $dst|$dst, $src}",
2854 [(set VR128:$dst,
2856 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2857 "movd\t{$src, $dst|$dst, $src}",
2858 [(set VR128:$dst,
2861 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2862 "movd\t{$src, $dst|$dst, $src}",
2863 [(set VR128:$dst,
2865 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2866 "movd\t{$src, $dst|$dst, $src}",
2867 [(set VR128:$dst,
2869 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2870 "mov{d|q}\t{$src, $dst|$dst, $src}",
2871 [(set VR128:$dst,
2873 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2874 "mov{d|q}\t{$src, $dst|$dst, $src}",
2875 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2879 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2880 "movd\t{$src, $dst|$dst, $src}",
2881 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2883 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2884 "movd\t{$src, $dst|$dst, $src}",
2885 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2887 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2888 "movd\t{$src, $dst|$dst, $src}",
2889 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2891 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2892 "movd\t{$src, $dst|$dst, $src}",
2893 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2896 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2897 "movd\t{$src, $dst|$dst, $src}",
2898 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2901 (ins i32mem:$dst, VR128:$src),
2902 "movd\t{$src, $dst|$dst, $src}",
2904 (iPTR 0))), addr:$dst)]>, VEX;
2905 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2906 "movd\t{$src, $dst|$dst, $src}",
2907 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2909 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2910 "movd\t{$src, $dst|$dst, $src}",
2912 (iPTR 0))), addr:$dst)]>;
2914 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2915 "mov{d|q}\t{$src, $dst|$dst, $src}",
2916 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2918 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2919 "movq\t{$src, $dst|$dst, $src}",
2920 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2922 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2923 "mov{d|q}\t{$src, $dst|$dst, $src}",
2924 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2925 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2926 "movq\t{$src, $dst|$dst, $src}",
2927 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2930 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2931 "movd\t{$src, $dst|$dst, $src}",
2932 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2933 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2934 "movd\t{$src, $dst|$dst, $src}",
2935 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2936 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2937 "movd\t{$src, $dst|$dst, $src}",
2938 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2939 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2940 "movd\t{$src, $dst|$dst, $src}",
2941 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2945 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2946 "movd\t{$src, $dst|$dst, $src}",
2947 [(set VR128:$dst, (v4i32 (X86vzmovl
2950 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2951 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2952 [(set VR128:$dst, (v2i64 (X86vzmovl
2957 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2958 "movd\t{$src, $dst|$dst, $src}",
2959 [(set VR128:$dst, (v4i32 (X86vzmovl
2961 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2962 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2963 [(set VR128:$dst, (v2i64 (X86vzmovl
2968 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2969 "movd\t{$src, $dst|$dst, $src}",
2970 [(set VR128:$dst,
2974 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2975 "movd\t{$src, $dst|$dst, $src}",
2976 [(set VR128:$dst,
2991 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2992 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
2993 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2994 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
2995 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2996 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
2997 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2998 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
2999 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3000 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3001 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3002 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3009 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3010 "vmovq\t{$src, $dst|$dst, $src}",
3011 [(set VR128:$dst,
3014 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3015 "movq\t{$src, $dst|$dst, $src}",
3016 [(set VR128:$dst,
3021 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3022 "movq\t{$src, $dst|$dst, $src}",
3024 (iPTR 0))), addr:$dst)]>, VEX;
3025 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3026 "movq\t{$src, $dst|$dst, $src}",
3028 (iPTR 0))), addr:$dst)]>;
3034 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3035 "movq\t{$src, $dst|$dst, $src}",
3036 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3037 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3038 "movq\t{$src, $dst|$dst, $src}",
3039 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3042 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3043 "vmovq\t{$src, $dst|$dst, $src}",
3044 [(set VR128:$dst,
3050 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3051 "movq\t{$src, $dst|$dst, $src}",
3052 [(set VR128:$dst,
3067 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3068 "vmovq\t{$src, $dst|$dst, $src}",
3069 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3072 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3073 "movq\t{$src, $dst|$dst, $src}",
3074 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3078 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3079 "vmovq\t{$src, $dst|$dst, $src}",
3080 [(set VR128:$dst, (v2i64 (X86vzmovl
3084 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3085 "movq\t{$src, $dst|$dst, $src}",
3086 [(set VR128:$dst, (v2i64 (X86vzmovl
3095 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3096 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3097 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3098 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3100 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3101 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3108 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3109 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3110 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3111 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3141 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3142 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3153 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3154 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3155 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3156 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3159 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3160 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3161 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3162 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3165 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3166 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3167 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3168 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3171 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3172 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3173 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3174 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3178 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3179 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3180 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3181 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3182 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3183 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3184 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3185 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3188 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3189 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3190 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3191 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3210 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3212 [(set VR128:$dst, (v4f32 (rep_frag
3214 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3215 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3216 [(set VR128:$dst, (rep_frag
3222 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3223 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3224 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3225 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3240 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3241 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3242 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3243 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3245 [(set VR128:$dst,
3251 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3252 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3254 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3255 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3268 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3269 "vlddqu\t{$src, $dst|$dst, $src}",
3270 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3271 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3272 "vlddqu\t{$src, $dst|$dst, $src}",
3273 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3275 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3276 "lddqu\t{$src, $dst|$dst, $src}",
3277 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3318 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3322 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3324 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3326 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3328 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3342 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3357 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3361 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3363 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3367 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3371 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3375 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3377 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3381 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3403 let Constraints = "$src1 = $dst" in {
3422 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3424 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3425 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3428 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3430 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3431 [(set VR128:$dst,
3461 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3464 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3465 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3466 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3468 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3471 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3472 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3473 [(set VR128:$dst,
3508 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3554 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3557 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3559 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3561 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3564 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3566 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3572 let Constraints = "$src1 = $dst" in
3879 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3880 (MOVAPSmr addr:$dst, VR128:$src)>;
3881 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3882 (MOVAPSmr addr:$dst, VR128:$src)>;
3883 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3884 (MOVAPSmr addr:$dst, VR128:$src)>;
3885 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3886 (MOVAPSmr addr:$dst, VR128:$src)>;
3887 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3888 (MOVUPSmr addr:$dst, VR128:$src)>;
3889 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3890 (MOVUPSmr addr:$dst, VR128:$src)>;
3891 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3892 (MOVUPSmr addr:$dst, VR128:$src)>;
3893 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3894 (MOVUPSmr addr:$dst, VR128:$src)>;
3909 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3910 (VMOVAPSmr addr:$dst, VR128:$src)>;
3911 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3912 (VMOVAPSmr addr:$dst, VR128:$src)>;
3913 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3914 (VMOVAPSmr addr:$dst, VR128:$src)>;
3915 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3916 (VMOVAPSmr addr:$dst, VR128:$src)>;
3917 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3918 (VMOVUPSmr addr:$dst, VR128:$src)>;
3919 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3920 (VMOVUPSmr addr:$dst, VR128:$src)>;
3921 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3922 (VMOVUPSmr addr:$dst, VR128:$src)>;
3923 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3924 (VMOVUPSmr addr:$dst, VR128:$src)>;
3935 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
3936 (VMOVAPSYmr addr:$dst, VR256:$src)>;
3937 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
3938 (VMOVAPSYmr addr:$dst, VR256:$src)>;
3939 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
3940 (VMOVUPSYmr addr:$dst, VR256:$src)>;
3941 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
3942 (VMOVUPSYmr addr:$dst, VR256:$src)>;
3950 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3952 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3954 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3956 [(set VR128:$dst,
4016 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4017 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4018 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4020 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4021 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4022 [(set VR128:$dst,
4056 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4057 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4058 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4061 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4062 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4063 [(set VR128:$dst, (IntId (bitconvert
4094 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4097 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4098 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4101 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4103 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4107 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4112 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4114 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4123 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4125 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4129 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4140 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4144 [(set GR32:$dst,
4147 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4149 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4151 addr:$dst)]>, OpSize;
4161 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4164 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4165 [(set GR64:$dst,
4168 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4170 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4172 addr:$dst)]>, OpSize, REX_W;
4183 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4186 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4187 [(set GR32:$dst,
4191 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4193 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4195 addr:$dst)]>, OpSize;
4200 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4202 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4210 addr:$dst),
4211 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4219 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4222 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4224 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4225 [(set VR128:$dst,
4227 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4230 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4232 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4233 [(set VR128:$dst,
4240 let Constraints = "$src1 = $dst" in
4244 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4247 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4249 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4250 [(set VR128:$dst,
4253 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4256 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4258 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4259 [(set VR128:$dst,
4266 let Constraints = "$src1 = $dst" in
4270 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4273 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4275 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4276 [(set VR128:$dst,
4279 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4282 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4285 [(set VR128:$dst,
4292 let Constraints = "$src1 = $dst" in
4300 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4303 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4305 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4306 [(set VR128:$dst,
4309 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4312 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4314 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4315 [(set VR128:$dst,
4321 let Constraints = "$src1 = $dst" in
4344 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4346 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4347 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4352 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4354 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4355 [(set RC:$dst,
4362 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4364 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4365 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4370 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4372 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4373 [(set RC:$dst,
4383 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4385 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4390 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4392 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4397 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4399 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4406 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4416 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4419 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4421 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4422 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4427 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4430 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4432 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4433 [(set VR128:$dst,
4439 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4442 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4444 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4445 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4450 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4453 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4455 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4456 [(set VR128:$dst,
4465 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4467 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4472 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4474 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4479 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4481 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4486 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4488 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4518 let Constraints = "$src1 = $dst" in
4582 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4583 "popcnt{w}\t{$src, $dst|$dst, $src}",
4584 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4585 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4586 "popcnt{w}\t{$src, $dst|$dst, $src}",
4587 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4589 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4590 "popcnt{l}\t{$src, $dst|$dst, $src}",
4591 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4592 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4593 "popcnt{l}\t{$src, $dst|$dst, $src}",
4594 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4596 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4597 "popcnt{q}\t{$src, $dst|$dst, $src}",
4598 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4599 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4600 "popcnt{q}\t{$src, $dst|$dst, $src}",
4601 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4608 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4610 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4611 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4612 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4615 [(set VR128:$dst,
4630 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4634 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4635 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4636 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4640 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4641 [(set VR128:$dst,
4672 let Constraints = "$src1 = $dst" in {
4696 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4699 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4700 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4701 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4703 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4708 [(set VR128:$dst, (OpNode VR128:$src1,
4715 let Constraints = "$src1 = $dst" in
4723 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4727 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4729 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4730 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4732 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4736 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4738 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4739 [(set RC:$dst,
4768 let Constraints = "$src1 = $dst" in {
4790 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4793 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4794 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4797 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4800 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4801 [(set RC:$dst,
4820 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4822 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4825 "\t{$src2, $dst|$dst, $src2}"),
4826 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4829 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4832 "\t{$src2, $dst|$dst, $src2}"),
4833 [(set VR128:$dst,
4847 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4848 "vmovntdqa\t{$src, $dst|$dst, $src}",
4849 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4851 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4852 "movntdqa\t{$src, $dst|$dst, $src}",
4853 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4863 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4866 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4868 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4870 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4873 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4874 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4875 [(set VR128:$dst,
4883 let Constraints = "$src1 = $dst" in
4897 def REG : PseudoI<(outs VR128:$dst),
4899 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4901 def MEM : PseudoI<(outs VR128:$dst),
4903 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4932 def REG : PseudoI<(outs VR128:$dst),
4934 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4936 def MEM : PseudoI<(outs VR128:$dst),
4938 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5052 let Constraints = "$src1 = $dst" in {
5053 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5056 [(set GR32:$dst,
5059 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5062 [(set GR32:$dst,
5064 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5067 [(set GR32:$dst,
5071 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5074 [(set GR32:$dst,
5077 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5080 [(set GR32:$dst,
5083 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5086 [(set GR32:$dst,
5088 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5091 [(set GR64:$dst,
5095 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5098 [(set GR64:$dst,
5101 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5104 [(set GR64:$dst,
5108 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5111 [(set GR64:$dst,
5122 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5125 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5126 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5127 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5129 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5132 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5133 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5134 [(set VR128:$dst,
5151 let Constraints = "$src1 = $dst" in {
5181 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5183 "vaesimc\t{$src1, $dst|$dst, $src1}",
5184 [(set VR128:$dst,
5187 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5189 "vaesimc\t{$src1, $dst|$dst, $src1}",
5190 [(set VR128:$dst,
5194 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5196 "aesimc\t{$src1, $dst|$dst, $src1}",
5197 [(set VR128:$dst,
5200 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5202 "aesimc\t{$src1, $dst|$dst, $src1}",
5203 [(set VR128:$dst,
5209 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5211 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5212 [(set VR128:$dst,
5215 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5217 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5218 [(set VR128:$dst,
5223 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5225 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5226 [(set VR128:$dst,
5229 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5231 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5232 [(set VR128:$dst,
5242 let Constraints = "$src1 = $dst" in {
5243 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5245 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5248 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5250 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5255 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5257 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5260 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5262 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5268 "dq {$src, $dst|$dst, $src}"),
5269 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5272 "dq {$src, $dst|$dst, $src}"),
5273 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5276 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5277 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5280 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5281 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5296 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5297 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5298 [(set RC:$dst, (Int addr:$src))]>, VEX;
5310 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5312 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5314 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5316 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5320 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5322 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5325 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5326 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5334 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5337 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5339 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5342 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5345 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5347 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5349 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5351 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5372 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5375 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5376 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5378 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5379 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5381 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5384 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5385 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5387 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5388 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5408 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5410 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5412 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5414 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5851 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5852 (MOVHPSmr addr:$dst, VR128:$src)>;
5854 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5855 (MOVHPDmr addr:$dst, VR128:$src)>;