192 #define INSN_RD(x)  ((x) << 25)  macro
253 #define WRY        (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
289     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |  in tcg_out_arith()
296     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |  in tcg_out_arithi()
303     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)  in tcg_out_arithc()
314     tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));  in tcg_out_sethi()
361     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |  in tcg_out_ld_raw()
371         tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |  in tcg_out_ld_ptr()
374         tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |  in tcg_out_ld_ptr()
382         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |  in tcg_out_ldst()
386         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |  in tcg_out_ldst()
395     tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |  in tcg_out_ldst_asi()
424     tcg_out32(s, RDY | INSN_RD(rd));  in tcg_out_rdy()
624         tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)  in tcg_out_setcond_i32()
651     tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)  in tcg_out_setcond_i64()
696     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |  in tcg_target_qemu_prologue()
698     tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |  in tcg_target_qemu_prologue()
784     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |  in tcg_out_qemu_ld()
996     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |  in tcg_out_qemu_st()
1124         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |  in tcg_out_op()
1126         tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |  in tcg_out_op()
1133             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |  in tcg_out_op()
1139             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |  in tcg_out_op()
1153             tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |  in tcg_out_op()