Lines Matching refs:CLG_
113 Addr CLG_(bb_base);
114 ULong* CLG_(cost_base);
847 idx, CLG_(bb_base) + current_ii->instr_offset, memline); in update_LL_use()
852 CLG_(current_state).collect, loaded->use_base); in update_LL_use()
854 if (CLG_(current_state).collect && loaded->use_base) { in update_LL_use()
864 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; in update_LL_use()
865 loaded->use_base = (CLG_(current_state).nonskipped) ? in update_LL_use()
866 CLG_(current_state).nonskipped->skipped : in update_LL_use()
867 CLG_(cost_base) + current_ii->cost_offset; in update_LL_use()
935 cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
940 CLG_(current_state).collect, loaded->use_base); \
942 if (CLG_(current_state).collect && loaded->use_base) { \
955 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \
956 loaded->use_base = (CLG_(current_state).nonskipped) ? \
957 CLG_(current_state).nonskipped->skipped : \
958 CLG_(cost_base) + current_ii->cost_offset; \
977 if (!CLG_(current_state).collect) return; in cacheuse_finish()
979 CLG_(bb_base) = 0; in cacheuse_finish()
981 CLG_(cost_base) = 0; in cacheuse_finish()
1054 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I0D()
1057 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes)); in log_1I0D()
1059 if (CLG_(current_state).collect) { in log_1I0D()
1062 if (CLG_(current_state).nonskipped) in log_1I0D()
1063 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I0D()
1065 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I0D()
1068 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I0D()
1079 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_2I0D()
1081 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_2I0D()
1084 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), in log_2I0D()
1085 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) ); in log_2I0D()
1087 if (!CLG_(current_state).collect) return; in log_2I0D()
1089 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); in log_2I0D()
1090 if (CLG_(current_state).nonskipped) { in log_2I0D()
1092 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_2I0D()
1100 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); in log_2I0D()
1102 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); in log_2I0D()
1112 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_3I0D()
1114 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_3I0D()
1116 Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size); in log_3I0D()
1119 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), in log_3I0D()
1120 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res), in log_3I0D()
1121 CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) ); in log_3I0D()
1123 if (!CLG_(current_state).collect) return; in log_3I0D()
1125 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); in log_3I0D()
1126 if (CLG_(current_state).nonskipped) { in log_3I0D()
1128 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_3I0D()
1136 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); in log_3I0D()
1138 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); in log_3I0D()
1140 CLG_(cost_base) + ii3->cost_offset + ii3->eventset->offset[EG_IR]); in log_3I0D()
1151 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dr()
1155 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), in log_1I1Dr()
1158 if (CLG_(current_state).collect) { in log_1I1Dr()
1161 if (CLG_(current_state).nonskipped) { in log_1I1Dr()
1162 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I1Dr()
1163 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); in log_1I1Dr()
1166 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I1Dr()
1167 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; in log_1I1Dr()
1171 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I1Dr()
1173 CLG_(current_state).cost + fullOffset(EG_DR) ); in log_1I1Dr()
1189 if (CLG_(current_state).collect) { in log_0I1Dr()
1192 if (CLG_(current_state).nonskipped) in log_0I1Dr()
1193 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); in log_0I1Dr()
1195 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; in log_0I1Dr()
1198 CLG_(current_state).cost + fullOffset(EG_DR) ); in log_0I1Dr()
1211 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dw()
1215 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), in log_1I1Dw()
1218 if (CLG_(current_state).collect) { in log_1I1Dw()
1221 if (CLG_(current_state).nonskipped) { in log_1I1Dw()
1222 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I1Dw()
1223 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); in log_1I1Dw()
1226 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I1Dw()
1227 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; in log_1I1Dw()
1231 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I1Dw()
1233 CLG_(current_state).cost + fullOffset(EG_DW) ); in log_1I1Dw()
1248 if (CLG_(current_state).collect) { in log_0I1Dw()
1251 if (CLG_(current_state).nonskipped) in log_0I1Dw()
1252 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); in log_0I1Dw()
1254 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; in log_0I1Dw()
1257 CLG_(current_state).cost + fullOffset(EG_DW) ); in log_0I1Dw()
1356 if (!CLG_(clo).simulate_cache) { in cachesim_post_clo_init()
1357 CLG_(cachesim).log_1I0D = 0; in cachesim_post_clo_init()
1358 CLG_(cachesim).log_1I0D_name = "(no function)"; in cachesim_post_clo_init()
1359 CLG_(cachesim).log_2I0D = 0; in cachesim_post_clo_init()
1360 CLG_(cachesim).log_2I0D_name = "(no function)"; in cachesim_post_clo_init()
1361 CLG_(cachesim).log_3I0D = 0; in cachesim_post_clo_init()
1362 CLG_(cachesim).log_3I0D_name = "(no function)"; in cachesim_post_clo_init()
1364 CLG_(cachesim).log_1I1Dr = 0; in cachesim_post_clo_init()
1365 CLG_(cachesim).log_1I1Dr_name = "(no function)"; in cachesim_post_clo_init()
1366 CLG_(cachesim).log_1I1Dw = 0; in cachesim_post_clo_init()
1367 CLG_(cachesim).log_1I1Dw_name = "(no function)"; in cachesim_post_clo_init()
1369 CLG_(cachesim).log_0I1Dr = 0; in cachesim_post_clo_init()
1370 CLG_(cachesim).log_0I1Dr_name = "(no function)"; in cachesim_post_clo_init()
1371 CLG_(cachesim).log_0I1Dw = 0; in cachesim_post_clo_init()
1372 CLG_(cachesim).log_0I1Dw_name = "(no function)"; in cachesim_post_clo_init()
1390 CLG_(cachesim).log_1I0D = log_1I0D; in cachesim_post_clo_init()
1391 CLG_(cachesim).log_1I0D_name = "log_1I0D"; in cachesim_post_clo_init()
1392 CLG_(cachesim).log_2I0D = log_2I0D; in cachesim_post_clo_init()
1393 CLG_(cachesim).log_2I0D_name = "log_2I0D"; in cachesim_post_clo_init()
1394 CLG_(cachesim).log_3I0D = log_3I0D; in cachesim_post_clo_init()
1395 CLG_(cachesim).log_3I0D_name = "log_3I0D"; in cachesim_post_clo_init()
1397 CLG_(cachesim).log_1I1Dr = log_1I1Dr; in cachesim_post_clo_init()
1398 CLG_(cachesim).log_1I1Dw = log_1I1Dw; in cachesim_post_clo_init()
1399 CLG_(cachesim).log_1I1Dr_name = "log_1I1Dr"; in cachesim_post_clo_init()
1400 CLG_(cachesim).log_1I1Dw_name = "log_1I1Dw"; in cachesim_post_clo_init()
1402 CLG_(cachesim).log_0I1Dr = log_0I1Dr; in cachesim_post_clo_init()
1403 CLG_(cachesim).log_0I1Dw = log_0I1Dw; in cachesim_post_clo_init()
1404 CLG_(cachesim).log_0I1Dr_name = "log_0I1Dr"; in cachesim_post_clo_init()
1405 CLG_(cachesim).log_0I1Dw_name = "log_0I1Dw"; in cachesim_post_clo_init()
1549 CLG_(clo).dump_instr = True; in cachesim_parse_opt()
1617 FullCost total = CLG_(total_cost), D_total = 0; in cachesim_printstat()
1657 D_total = CLG_(get_eventset_cost)( CLG_(sets).full ); in cachesim_printstat()
1658 CLG_(init_cost)( CLG_(sets).full, D_total); in cachesim_printstat()
1660 CLG_(copy_cost)( CLG_(get_event_set)(EG_DR), D_total, total + fullOffset(EG_DR) ); in cachesim_printstat()
1661 CLG_(add_cost) ( CLG_(get_event_set)(EG_DW), D_total, total + fullOffset(EG_DW) ); in cachesim_printstat()
1752 struct event_sets CLG_(sets);
1754 void CLG_(init_eventsets)() in CLG_() function
1759 CLG_(register_event_group4)(EG_USE, in CLG_()
1762 if (!CLG_(clo).simulate_cache) in CLG_()
1763 CLG_(register_event_group)(EG_IR, "Ir"); in CLG_()
1765 CLG_(register_event_group3)(EG_IR, "Ir", "I1mr", "ILmr"); in CLG_()
1766 CLG_(register_event_group3)(EG_DR, "Dr", "D1mr", "DLmr"); in CLG_()
1767 CLG_(register_event_group3)(EG_DW, "Dw", "D1mw", "DLmw"); in CLG_()
1770 CLG_(register_event_group4)(EG_IR, "Ir", "I1mr", "ILmr", "ILdmr"); in CLG_()
1771 CLG_(register_event_group4)(EG_DR, "Dr", "D1mr", "DLmr", "DLdmr"); in CLG_()
1772 CLG_(register_event_group4)(EG_DW, "Dw", "D1mw", "DLmw", "DLdmw"); in CLG_()
1775 if (CLG_(clo).simulate_branch) { in CLG_()
1776 CLG_(register_event_group2)(EG_BC, "Bc", "Bcm"); in CLG_()
1777 CLG_(register_event_group2)(EG_BI, "Bi", "Bim"); in CLG_()
1780 if (CLG_(clo).collect_bus) in CLG_()
1781 CLG_(register_event_group)(EG_BUS, "Ge"); in CLG_()
1783 if (CLG_(clo).collect_alloc) in CLG_()
1784 CLG_(register_event_group2)(EG_ALLOC, "allocCount", "allocSize"); in CLG_()
1786 if (CLG_(clo).collect_systime) in CLG_()
1787 CLG_(register_event_group2)(EG_SYS, "sysCount", "sysTime"); in CLG_()
1790 CLG_(sets).base = CLG_(get_event_set2)(EG_USE, EG_IR); in CLG_()
1793 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).base, EG_DR, EG_DW); in CLG_()
1794 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_BC, EG_BI); in CLG_()
1795 CLG_(sets).full = CLG_(add_event_group) (CLG_(sets).full, EG_BUS); in CLG_()
1796 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_ALLOC, EG_SYS); in CLG_()
1800 CLG_(print_eventset)(-2, CLG_(sets).base); in CLG_()
1801 CLG_(print_eventset)(-2, CLG_(sets).full); in CLG_()
1805 CLG_(dumpmap) = CLG_(get_eventmapping)(CLG_(sets).full); in CLG_()
1806 CLG_(append_event)(CLG_(dumpmap), "Ir"); in CLG_()
1807 CLG_(append_event)(CLG_(dumpmap), "Dr"); in CLG_()
1808 CLG_(append_event)(CLG_(dumpmap), "Dw"); in CLG_()
1809 CLG_(append_event)(CLG_(dumpmap), "I1mr"); in CLG_()
1810 CLG_(append_event)(CLG_(dumpmap), "D1mr"); in CLG_()
1811 CLG_(append_event)(CLG_(dumpmap), "D1mw"); in CLG_()
1812 CLG_(append_event)(CLG_(dumpmap), "ILmr"); in CLG_()
1813 CLG_(append_event)(CLG_(dumpmap), "DLmr"); in CLG_()
1814 CLG_(append_event)(CLG_(dumpmap), "DLmw"); in CLG_()
1815 CLG_(append_event)(CLG_(dumpmap), "ILdmr"); in CLG_()
1816 CLG_(append_event)(CLG_(dumpmap), "DLdmr"); in CLG_()
1817 CLG_(append_event)(CLG_(dumpmap), "DLdmw"); in CLG_()
1818 CLG_(append_event)(CLG_(dumpmap), "Bc"); in CLG_()
1819 CLG_(append_event)(CLG_(dumpmap), "Bcm"); in CLG_()
1820 CLG_(append_event)(CLG_(dumpmap), "Bi"); in CLG_()
1821 CLG_(append_event)(CLG_(dumpmap), "Bim"); in CLG_()
1822 CLG_(append_event)(CLG_(dumpmap), "AcCost1"); in CLG_()
1823 CLG_(append_event)(CLG_(dumpmap), "SpLoss1"); in CLG_()
1824 CLG_(append_event)(CLG_(dumpmap), "AcCost2"); in CLG_()
1825 CLG_(append_event)(CLG_(dumpmap), "SpLoss2"); in CLG_()
1826 CLG_(append_event)(CLG_(dumpmap), "Ge"); in CLG_()
1827 CLG_(append_event)(CLG_(dumpmap), "allocCount"); in CLG_()
1828 CLG_(append_event)(CLG_(dumpmap), "allocSize"); in CLG_()
1829 CLG_(append_event)(CLG_(dumpmap), "sysCount"); in CLG_()
1830 CLG_(append_event)(CLG_(dumpmap), "sysTime"); in CLG_()
1838 if (!CLG_(clo).simulate_cache) in cachesim_add_icost()
1842 CLG_(add_and_zero_cost2)( CLG_(sets).full, cost, in cachesim_add_icost()
1857 struct cachesim_if CLG_(cachesim) = {