1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
16 // types.
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
20 //
21 //===----------------------------------------------------------------------===//
22
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 using namespace llvm;
29
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
33
ScalarizeVectorResult(SDNode * N,unsigned ResNo)34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
36 N->dump(&DAG);
37 dbgs() << "\n");
38 SDValue R = SDValue();
39
40 switch (N->getOpcode()) {
41 default:
42 #ifndef NDEBUG
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
44 N->dump(&DAG);
45 dbgs() << "\n";
46 #endif
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
48
49 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
54 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
55 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
57 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
60 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
61 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
62 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
63 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
64 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
65 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
66
67 case ISD::ANY_EXTEND:
68 case ISD::CTLZ:
69 case ISD::CTPOP:
70 case ISD::CTTZ:
71 case ISD::FABS:
72 case ISD::FCEIL:
73 case ISD::FCOS:
74 case ISD::FEXP:
75 case ISD::FEXP2:
76 case ISD::FFLOOR:
77 case ISD::FLOG:
78 case ISD::FLOG10:
79 case ISD::FLOG2:
80 case ISD::FNEARBYINT:
81 case ISD::FNEG:
82 case ISD::FP_EXTEND:
83 case ISD::FP_TO_SINT:
84 case ISD::FP_TO_UINT:
85 case ISD::FRINT:
86 case ISD::FSIN:
87 case ISD::FSQRT:
88 case ISD::FTRUNC:
89 case ISD::SIGN_EXTEND:
90 case ISD::SINT_TO_FP:
91 case ISD::TRUNCATE:
92 case ISD::UINT_TO_FP:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
95 break;
96
97 case ISD::ADD:
98 case ISD::AND:
99 case ISD::FADD:
100 case ISD::FDIV:
101 case ISD::FMUL:
102 case ISD::FPOW:
103 case ISD::FREM:
104 case ISD::FSUB:
105 case ISD::MUL:
106 case ISD::OR:
107 case ISD::SDIV:
108 case ISD::SREM:
109 case ISD::SUB:
110 case ISD::UDIV:
111 case ISD::UREM:
112 case ISD::XOR:
113 case ISD::SHL:
114 case ISD::SRA:
115 case ISD::SRL:
116 R = ScalarizeVecRes_BinOp(N);
117 break;
118 }
119
120 // If R is null, the sub-method took care of registering the result.
121 if (R.getNode())
122 SetScalarizedVector(SDValue(N, ResNo), R);
123 }
124
ScalarizeVecRes_BinOp(SDNode * N)125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
129 LHS.getValueType(), LHS, RHS);
130 }
131
ScalarizeVecRes_BITCAST(SDNode * N)132 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
133 EVT NewVT = N->getValueType(0).getVectorElementType();
134 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
135 NewVT, N->getOperand(0));
136 }
137
ScalarizeVecRes_CONVERT_RNDSAT(SDNode * N)138 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
139 EVT NewVT = N->getValueType(0).getVectorElementType();
140 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
141 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
142 Op0, DAG.getValueType(NewVT),
143 DAG.getValueType(Op0.getValueType()),
144 N->getOperand(3),
145 N->getOperand(4),
146 cast<CvtRndSatSDNode>(N)->getCvtCode());
147 }
148
ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode * N)149 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
151 N->getValueType(0).getVectorElementType(),
152 N->getOperand(0), N->getOperand(1));
153 }
154
ScalarizeVecRes_FP_ROUND(SDNode * N)155 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
156 EVT NewVT = N->getValueType(0).getVectorElementType();
157 SDValue Op = GetScalarizedVector(N->getOperand(0));
158 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
159 NewVT, Op, N->getOperand(1));
160 }
161
ScalarizeVecRes_FPOWI(SDNode * N)162 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
165 Op.getValueType(), Op, N->getOperand(1));
166 }
167
ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode * N)168 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
169 // The value to insert may have a wider type than the vector element type,
170 // so be sure to truncate it to the element type if necessary.
171 SDValue Op = N->getOperand(1);
172 EVT EltVT = N->getValueType(0).getVectorElementType();
173 if (Op.getValueType() != EltVT)
174 // FIXME: Can this happen for floating point types?
175 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
176 return Op;
177 }
178
ScalarizeVecRes_LOAD(LoadSDNode * N)179 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
180 assert(N->isUnindexed() && "Indexed vector load?");
181
182 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
183 N->getExtensionType(),
184 N->getValueType(0).getVectorElementType(),
185 N->getDebugLoc(),
186 N->getChain(), N->getBasePtr(),
187 DAG.getUNDEF(N->getBasePtr().getValueType()),
188 N->getPointerInfo(),
189 N->getMemoryVT().getVectorElementType(),
190 N->isVolatile(), N->isNonTemporal(),
191 N->getOriginalAlignment());
192
193 // Legalized the chain result - switch anything that used the old chain to
194 // use the new one.
195 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
196 return Result;
197 }
198
ScalarizeVecRes_UnaryOp(SDNode * N)199 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
200 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
201 EVT DestVT = N->getValueType(0).getVectorElementType();
202 SDValue Op = GetScalarizedVector(N->getOperand(0));
203 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
204 }
205
ScalarizeVecRes_InregOp(SDNode * N)206 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
207 EVT EltVT = N->getValueType(0).getVectorElementType();
208 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
209 SDValue LHS = GetScalarizedVector(N->getOperand(0));
210 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
211 LHS, DAG.getValueType(ExtVT));
212 }
213
ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode * N)214 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
215 // If the operand is wider than the vector element type then it is implicitly
216 // truncated. Make that explicit here.
217 EVT EltVT = N->getValueType(0).getVectorElementType();
218 SDValue InOp = N->getOperand(0);
219 if (InOp.getValueType() != EltVT)
220 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
221 return InOp;
222 }
223
ScalarizeVecRes_SELECT(SDNode * N)224 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
225 SDValue LHS = GetScalarizedVector(N->getOperand(1));
226 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
227 LHS.getValueType(), N->getOperand(0), LHS,
228 GetScalarizedVector(N->getOperand(2)));
229 }
230
ScalarizeVecRes_SELECT_CC(SDNode * N)231 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
232 SDValue LHS = GetScalarizedVector(N->getOperand(2));
233 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
234 N->getOperand(0), N->getOperand(1),
235 LHS, GetScalarizedVector(N->getOperand(3)),
236 N->getOperand(4));
237 }
238
ScalarizeVecRes_SETCC(SDNode * N)239 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
240 SDValue LHS = GetScalarizedVector(N->getOperand(0));
241 SDValue RHS = GetScalarizedVector(N->getOperand(1));
242 DebugLoc DL = N->getDebugLoc();
243
244 // Turn it into a scalar SETCC.
245 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
246 }
247
ScalarizeVecRes_UNDEF(SDNode * N)248 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
249 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
250 }
251
ScalarizeVecRes_VECTOR_SHUFFLE(SDNode * N)252 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
253 // Figure out if the scalar is the LHS or RHS and return it.
254 SDValue Arg = N->getOperand(2).getOperand(0);
255 if (Arg.getOpcode() == ISD::UNDEF)
256 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
257 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
258 return GetScalarizedVector(N->getOperand(Op));
259 }
260
ScalarizeVecRes_VSETCC(SDNode * N)261 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
262 SDValue LHS = GetScalarizedVector(N->getOperand(0));
263 SDValue RHS = GetScalarizedVector(N->getOperand(1));
264 EVT NVT = N->getValueType(0).getVectorElementType();
265 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
266 DebugLoc DL = N->getDebugLoc();
267
268 // Turn it into a scalar SETCC.
269 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
270
271 // VSETCC always returns a sign-extended value, while SETCC may not. The
272 // SETCC result type may not match the vector element type. Correct these.
273 if (NVT.bitsLE(SVT)) {
274 // The SETCC result type is bigger than the vector element type.
275 // Ensure the SETCC result is sign-extended.
276 if (TLI.getBooleanContents() !=
277 TargetLowering::ZeroOrNegativeOneBooleanContent)
278 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
279 DAG.getValueType(MVT::i1));
280 // Truncate to the final type.
281 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
282 }
283
284 // The SETCC result type is smaller than the vector element type.
285 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
286 if (TLI.getBooleanContents() !=
287 TargetLowering::ZeroOrNegativeOneBooleanContent)
288 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
289 // Sign extend to the final type.
290 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
291 }
292
293
294 //===----------------------------------------------------------------------===//
295 // Operand Vector Scalarization <1 x ty> -> ty.
296 //===----------------------------------------------------------------------===//
297
ScalarizeVectorOperand(SDNode * N,unsigned OpNo)298 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
300 N->dump(&DAG);
301 dbgs() << "\n");
302 SDValue Res = SDValue();
303
304 if (Res.getNode() == 0) {
305 switch (N->getOpcode()) {
306 default:
307 #ifndef NDEBUG
308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
309 N->dump(&DAG);
310 dbgs() << "\n";
311 #endif
312 llvm_unreachable("Do not know how to scalarize this operator's operand!");
313 case ISD::BITCAST:
314 Res = ScalarizeVecOp_BITCAST(N);
315 break;
316 case ISD::CONCAT_VECTORS:
317 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
318 break;
319 case ISD::EXTRACT_VECTOR_ELT:
320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
321 break;
322 case ISD::STORE:
323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
324 break;
325 }
326 }
327
328 // If the result is null, the sub-method took care of registering results etc.
329 if (!Res.getNode()) return false;
330
331 // If the result is N, the sub-method updated N in place. Tell the legalizer
332 // core about this.
333 if (Res.getNode() == N)
334 return true;
335
336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
337 "Invalid operand expansion");
338
339 ReplaceValueWith(SDValue(N, 0), Res);
340 return false;
341 }
342
343 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
344 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
ScalarizeVecOp_BITCAST(SDNode * N)345 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
346 SDValue Elt = GetScalarizedVector(N->getOperand(0));
347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
348 N->getValueType(0), Elt);
349 }
350
351 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
352 /// use a BUILD_VECTOR instead.
ScalarizeVecOp_CONCAT_VECTORS(SDNode * N)353 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
354 SmallVector<SDValue, 8> Ops(N->getNumOperands());
355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
356 Ops[i] = GetScalarizedVector(N->getOperand(i));
357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
358 &Ops[0], Ops.size());
359 }
360
361 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
362 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
363 /// index.
ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode * N)364 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
365 SDValue Res = GetScalarizedVector(N->getOperand(0));
366 if (Res.getValueType() != N->getValueType(0))
367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
368 Res);
369 return Res;
370 }
371
372 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
373 /// scalarized, it must be <1 x ty>. Just store the element.
ScalarizeVecOp_STORE(StoreSDNode * N,unsigned OpNo)374 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
375 assert(N->isUnindexed() && "Indexed store of one-element vector?");
376 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
377 DebugLoc dl = N->getDebugLoc();
378
379 if (N->isTruncatingStore())
380 return DAG.getTruncStore(N->getChain(), dl,
381 GetScalarizedVector(N->getOperand(1)),
382 N->getBasePtr(), N->getPointerInfo(),
383 N->getMemoryVT().getVectorElementType(),
384 N->isVolatile(), N->isNonTemporal(),
385 N->getAlignment());
386
387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
388 N->getBasePtr(), N->getPointerInfo(),
389 N->isVolatile(), N->isNonTemporal(),
390 N->getOriginalAlignment());
391 }
392
393
394 //===----------------------------------------------------------------------===//
395 // Result Vector Splitting
396 //===----------------------------------------------------------------------===//
397
398 /// SplitVectorResult - This method is called when the specified result of the
399 /// specified node is found to need vector splitting. At this point, the node
400 /// may also have invalid operands or may have other results that need
401 /// legalization, we just know that (at least) one result needs vector
402 /// splitting.
SplitVectorResult(SDNode * N,unsigned ResNo)403 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
404 DEBUG(dbgs() << "Split node result: ";
405 N->dump(&DAG);
406 dbgs() << "\n");
407 SDValue Lo, Hi;
408
409 switch (N->getOpcode()) {
410 default:
411 #ifndef NDEBUG
412 dbgs() << "SplitVectorResult #" << ResNo << ": ";
413 N->dump(&DAG);
414 dbgs() << "\n";
415 #endif
416 llvm_unreachable("Do not know how to split the result of this operator!");
417
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
419 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
420 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
421 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
422 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
423 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
424 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
425 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
426 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
427 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
428 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
429 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
430 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
431 case ISD::LOAD:
432 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
433 break;
434 case ISD::SETCC:
435 case ISD::VSETCC:
436 SplitVecRes_SETCC(N, Lo, Hi);
437 break;
438 case ISD::VECTOR_SHUFFLE:
439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
440 break;
441
442 case ISD::ANY_EXTEND:
443 case ISD::CONVERT_RNDSAT:
444 case ISD::CTLZ:
445 case ISD::CTPOP:
446 case ISD::CTTZ:
447 case ISD::FABS:
448 case ISD::FCEIL:
449 case ISD::FCOS:
450 case ISD::FEXP:
451 case ISD::FEXP2:
452 case ISD::FFLOOR:
453 case ISD::FLOG:
454 case ISD::FLOG10:
455 case ISD::FLOG2:
456 case ISD::FNEARBYINT:
457 case ISD::FNEG:
458 case ISD::FP_EXTEND:
459 case ISD::FP_ROUND:
460 case ISD::FP_TO_SINT:
461 case ISD::FP_TO_UINT:
462 case ISD::FRINT:
463 case ISD::FSIN:
464 case ISD::FSQRT:
465 case ISD::FTRUNC:
466 case ISD::SIGN_EXTEND:
467 case ISD::SINT_TO_FP:
468 case ISD::TRUNCATE:
469 case ISD::UINT_TO_FP:
470 case ISD::ZERO_EXTEND:
471 SplitVecRes_UnaryOp(N, Lo, Hi);
472 break;
473
474 case ISD::ADD:
475 case ISD::SUB:
476 case ISD::MUL:
477 case ISD::FADD:
478 case ISD::FSUB:
479 case ISD::FMUL:
480 case ISD::SDIV:
481 case ISD::UDIV:
482 case ISD::FDIV:
483 case ISD::FPOW:
484 case ISD::AND:
485 case ISD::OR:
486 case ISD::XOR:
487 case ISD::SHL:
488 case ISD::SRA:
489 case ISD::SRL:
490 case ISD::UREM:
491 case ISD::SREM:
492 case ISD::FREM:
493 SplitVecRes_BinOp(N, Lo, Hi);
494 break;
495 }
496
497 // If Lo/Hi is null, the sub-method took care of registering results etc.
498 if (Lo.getNode())
499 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
500 }
501
SplitVecRes_BinOp(SDNode * N,SDValue & Lo,SDValue & Hi)502 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
503 SDValue &Hi) {
504 SDValue LHSLo, LHSHi;
505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
506 SDValue RHSLo, RHSHi;
507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
508 DebugLoc dl = N->getDebugLoc();
509
510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
512 }
513
SplitVecRes_BITCAST(SDNode * N,SDValue & Lo,SDValue & Hi)514 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
515 SDValue &Hi) {
516 // We know the result is a vector. The input may be either a vector or a
517 // scalar value.
518 EVT LoVT, HiVT;
519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
520 DebugLoc dl = N->getDebugLoc();
521
522 SDValue InOp = N->getOperand(0);
523 EVT InVT = InOp.getValueType();
524
525 // Handle some special cases efficiently.
526 switch (getTypeAction(InVT)) {
527 default:
528 assert(false && "Unknown type action!");
529 case TargetLowering::TypeLegal:
530 case TargetLowering::TypePromoteInteger:
531 case TargetLowering::TypeSoftenFloat:
532 case TargetLowering::TypeScalarizeVector:
533 break;
534 case TargetLowering::TypeExpandInteger:
535 case TargetLowering::TypeExpandFloat:
536 // A scalar to vector conversion, where the scalar needs expansion.
537 // If the vector is being split in two then we can just convert the
538 // expanded pieces.
539 if (LoVT == HiVT) {
540 GetExpandedOp(InOp, Lo, Hi);
541 if (TLI.isBigEndian())
542 std::swap(Lo, Hi);
543 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
544 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
545 return;
546 }
547 break;
548 case TargetLowering::TypeSplitVector:
549 // If the input is a vector that needs to be split, convert each split
550 // piece of the input now.
551 GetSplitVector(InOp, Lo, Hi);
552 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
553 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
554 return;
555 }
556
557 // In the general case, convert the input to an integer and split it by hand.
558 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
559 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
560 if (TLI.isBigEndian())
561 std::swap(LoIntVT, HiIntVT);
562
563 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
564
565 if (TLI.isBigEndian())
566 std::swap(Lo, Hi);
567 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
568 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
569 }
570
SplitVecRes_BUILD_VECTOR(SDNode * N,SDValue & Lo,SDValue & Hi)571 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
572 SDValue &Hi) {
573 EVT LoVT, HiVT;
574 DebugLoc dl = N->getDebugLoc();
575 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
576 unsigned LoNumElts = LoVT.getVectorNumElements();
577 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
578 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
579
580 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
581 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
582 }
583
SplitVecRes_CONCAT_VECTORS(SDNode * N,SDValue & Lo,SDValue & Hi)584 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
585 SDValue &Hi) {
586 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
587 DebugLoc dl = N->getDebugLoc();
588 unsigned NumSubvectors = N->getNumOperands() / 2;
589 if (NumSubvectors == 1) {
590 Lo = N->getOperand(0);
591 Hi = N->getOperand(1);
592 return;
593 }
594
595 EVT LoVT, HiVT;
596 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
597
598 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
599 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
600
601 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
602 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
603 }
604
SplitVecRes_EXTRACT_SUBVECTOR(SDNode * N,SDValue & Lo,SDValue & Hi)605 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
606 SDValue &Hi) {
607 SDValue Vec = N->getOperand(0);
608 SDValue Idx = N->getOperand(1);
609 DebugLoc dl = N->getDebugLoc();
610
611 EVT LoVT, HiVT;
612 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
613
614 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
615 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
616 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
617 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
618 }
619
SplitVecRes_FPOWI(SDNode * N,SDValue & Lo,SDValue & Hi)620 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
621 SDValue &Hi) {
622 DebugLoc dl = N->getDebugLoc();
623 GetSplitVector(N->getOperand(0), Lo, Hi);
624 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
625 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
626 }
627
SplitVecRes_InregOp(SDNode * N,SDValue & Lo,SDValue & Hi)628 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
629 SDValue &Hi) {
630 SDValue LHSLo, LHSHi;
631 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
632 DebugLoc dl = N->getDebugLoc();
633
634 EVT LoVT, HiVT;
635 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
636
637 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
638 DAG.getValueType(LoVT));
639 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
640 DAG.getValueType(HiVT));
641 }
642
SplitVecRes_INSERT_VECTOR_ELT(SDNode * N,SDValue & Lo,SDValue & Hi)643 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
644 SDValue &Hi) {
645 SDValue Vec = N->getOperand(0);
646 SDValue Elt = N->getOperand(1);
647 SDValue Idx = N->getOperand(2);
648 DebugLoc dl = N->getDebugLoc();
649 GetSplitVector(Vec, Lo, Hi);
650
651 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
652 unsigned IdxVal = CIdx->getZExtValue();
653 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
654 if (IdxVal < LoNumElts)
655 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
656 Lo.getValueType(), Lo, Elt, Idx);
657 else
658 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
659 DAG.getIntPtrConstant(IdxVal - LoNumElts));
660 return;
661 }
662
663 // Spill the vector to the stack.
664 EVT VecVT = Vec.getValueType();
665 EVT EltVT = VecVT.getVectorElementType();
666 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
667 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
668 MachinePointerInfo(), false, false, 0);
669
670 // Store the new element. This may be larger than the vector element type,
671 // so use a truncating store.
672 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
673 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
674 unsigned Alignment =
675 TLI.getTargetData()->getPrefTypeAlignment(VecType);
676 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
677 false, false, 0);
678
679 // Load the Lo part from the stack slot.
680 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
681 false, false, 0);
682
683 // Increment the pointer to the other part.
684 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
685 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
686 DAG.getIntPtrConstant(IncrementSize));
687
688 // Load the Hi part from the stack slot.
689 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
690 false, false, MinAlign(Alignment, IncrementSize));
691 }
692
SplitVecRes_SCALAR_TO_VECTOR(SDNode * N,SDValue & Lo,SDValue & Hi)693 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
694 SDValue &Hi) {
695 EVT LoVT, HiVT;
696 DebugLoc dl = N->getDebugLoc();
697 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
698 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
699 Hi = DAG.getUNDEF(HiVT);
700 }
701
SplitVecRes_LOAD(LoadSDNode * LD,SDValue & Lo,SDValue & Hi)702 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
703 SDValue &Hi) {
704 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
705 EVT LoVT, HiVT;
706 DebugLoc dl = LD->getDebugLoc();
707 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
708
709 ISD::LoadExtType ExtType = LD->getExtensionType();
710 SDValue Ch = LD->getChain();
711 SDValue Ptr = LD->getBasePtr();
712 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
713 EVT MemoryVT = LD->getMemoryVT();
714 unsigned Alignment = LD->getOriginalAlignment();
715 bool isVolatile = LD->isVolatile();
716 bool isNonTemporal = LD->isNonTemporal();
717
718 EVT LoMemVT, HiMemVT;
719 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
720
721 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
722 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
723 Alignment);
724
725 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
726 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
727 DAG.getIntPtrConstant(IncrementSize));
728 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
729 LD->getPointerInfo().getWithOffset(IncrementSize),
730 HiMemVT, isVolatile, isNonTemporal, Alignment);
731
732 // Build a factor node to remember that this load is independent of the
733 // other one.
734 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
735 Hi.getValue(1));
736
737 // Legalized the chain result - switch anything that used the old chain to
738 // use the new one.
739 ReplaceValueWith(SDValue(LD, 1), Ch);
740 }
741
SplitVecRes_SETCC(SDNode * N,SDValue & Lo,SDValue & Hi)742 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
743 EVT LoVT, HiVT;
744 DebugLoc DL = N->getDebugLoc();
745 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
746
747 // Split the input.
748 EVT InVT = N->getOperand(0).getValueType();
749 SDValue LL, LH, RL, RH;
750 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
751 LoVT.getVectorNumElements());
752 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
753 DAG.getIntPtrConstant(0));
754 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
755 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
756
757 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
758 DAG.getIntPtrConstant(0));
759 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
760 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
761
762 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
763 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
764 }
765
SplitVecRes_UnaryOp(SDNode * N,SDValue & Lo,SDValue & Hi)766 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
767 SDValue &Hi) {
768 // Get the dest types - they may not match the input types, e.g. int_to_fp.
769 EVT LoVT, HiVT;
770 DebugLoc dl = N->getDebugLoc();
771 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
772
773 // Split the input.
774 EVT InVT = N->getOperand(0).getValueType();
775 switch (getTypeAction(InVT)) {
776 default: llvm_unreachable("Unexpected type action!");
777 case TargetLowering::TypeLegal: {
778 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
779 LoVT.getVectorNumElements());
780 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
781 DAG.getIntPtrConstant(0));
782 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
783 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
784 break;
785 }
786 case TargetLowering::TypePromoteInteger: {
787 SDValue InOp = GetPromotedInteger(N->getOperand(0));
788 EVT InNVT = EVT::getVectorVT(*DAG.getContext(),
789 InOp.getValueType().getVectorElementType(),
790 LoVT.getVectorNumElements());
791 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
792 DAG.getIntPtrConstant(0));
793 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
794 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
795 break;
796 }
797 case TargetLowering::TypeSplitVector:
798 GetSplitVector(N->getOperand(0), Lo, Hi);
799 break;
800 case TargetLowering::TypeWidenVector: {
801 // If the result needs to be split and the input needs to be widened,
802 // the two types must have different lengths. Use the widened result
803 // and extract from it to do the split.
804 SDValue InOp = GetWidenedVector(N->getOperand(0));
805 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
806 LoVT.getVectorNumElements());
807 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
808 DAG.getIntPtrConstant(0));
809 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
810 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
811 break;
812 }
813 }
814
815 if (N->getOpcode() == ISD::FP_ROUND) {
816 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
817 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
818 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
819 SDValue DTyOpLo = DAG.getValueType(LoVT);
820 SDValue DTyOpHi = DAG.getValueType(HiVT);
821 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
822 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
823 SDValue RndOp = N->getOperand(3);
824 SDValue SatOp = N->getOperand(4);
825 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
826 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
827 CvtCode);
828 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
829 CvtCode);
830 } else {
831 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
832 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
833 }
834 }
835
SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode * N,SDValue & Lo,SDValue & Hi)836 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
837 SDValue &Lo, SDValue &Hi) {
838 // The low and high parts of the original input give four input vectors.
839 SDValue Inputs[4];
840 DebugLoc dl = N->getDebugLoc();
841 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
842 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
843 EVT NewVT = Inputs[0].getValueType();
844 unsigned NewElts = NewVT.getVectorNumElements();
845
846 // If Lo or Hi uses elements from at most two of the four input vectors, then
847 // express it as a vector shuffle of those two inputs. Otherwise extract the
848 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
849 SmallVector<int, 16> Ops;
850 for (unsigned High = 0; High < 2; ++High) {
851 SDValue &Output = High ? Hi : Lo;
852
853 // Build a shuffle mask for the output, discovering on the fly which
854 // input vectors to use as shuffle operands (recorded in InputUsed).
855 // If building a suitable shuffle vector proves too hard, then bail
856 // out with useBuildVector set.
857 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
858 unsigned FirstMaskIdx = High * NewElts;
859 bool useBuildVector = false;
860 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
861 // The mask element. This indexes into the input.
862 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
863
864 // The input vector this mask element indexes into.
865 unsigned Input = (unsigned)Idx / NewElts;
866
867 if (Input >= array_lengthof(Inputs)) {
868 // The mask element does not index into any input vector.
869 Ops.push_back(-1);
870 continue;
871 }
872
873 // Turn the index into an offset from the start of the input vector.
874 Idx -= Input * NewElts;
875
876 // Find or create a shuffle vector operand to hold this input.
877 unsigned OpNo;
878 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
879 if (InputUsed[OpNo] == Input) {
880 // This input vector is already an operand.
881 break;
882 } else if (InputUsed[OpNo] == -1U) {
883 // Create a new operand for this input vector.
884 InputUsed[OpNo] = Input;
885 break;
886 }
887 }
888
889 if (OpNo >= array_lengthof(InputUsed)) {
890 // More than two input vectors used! Give up on trying to create a
891 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
892 useBuildVector = true;
893 break;
894 }
895
896 // Add the mask index for the new shuffle vector.
897 Ops.push_back(Idx + OpNo * NewElts);
898 }
899
900 if (useBuildVector) {
901 EVT EltVT = NewVT.getVectorElementType();
902 SmallVector<SDValue, 16> SVOps;
903
904 // Extract the input elements by hand.
905 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
906 // The mask element. This indexes into the input.
907 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
908
909 // The input vector this mask element indexes into.
910 unsigned Input = (unsigned)Idx / NewElts;
911
912 if (Input >= array_lengthof(Inputs)) {
913 // The mask element is "undef" or indexes off the end of the input.
914 SVOps.push_back(DAG.getUNDEF(EltVT));
915 continue;
916 }
917
918 // Turn the index into an offset from the start of the input vector.
919 Idx -= Input * NewElts;
920
921 // Extract the vector element by hand.
922 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
923 Inputs[Input], DAG.getIntPtrConstant(Idx)));
924 }
925
926 // Construct the Lo/Hi output using a BUILD_VECTOR.
927 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
928 } else if (InputUsed[0] == -1U) {
929 // No input vectors were used! The result is undefined.
930 Output = DAG.getUNDEF(NewVT);
931 } else {
932 SDValue Op0 = Inputs[InputUsed[0]];
933 // If only one input was used, use an undefined vector for the other.
934 SDValue Op1 = InputUsed[1] == -1U ?
935 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
936 // At least one input vector was used. Create a new shuffle vector.
937 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
938 }
939
940 Ops.clear();
941 }
942 }
943
944
945 //===----------------------------------------------------------------------===//
946 // Operand Vector Splitting
947 //===----------------------------------------------------------------------===//
948
949 /// SplitVectorOperand - This method is called when the specified operand of the
950 /// specified node is found to need vector splitting. At this point, all of the
951 /// result types of the node are known to be legal, but other operands of the
952 /// node may need legalization as well as the specified one.
SplitVectorOperand(SDNode * N,unsigned OpNo)953 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
954 DEBUG(dbgs() << "Split node operand: ";
955 N->dump(&DAG);
956 dbgs() << "\n");
957 SDValue Res = SDValue();
958
959 if (Res.getNode() == 0) {
960 switch (N->getOpcode()) {
961 default:
962 #ifndef NDEBUG
963 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
964 N->dump(&DAG);
965 dbgs() << "\n";
966 #endif
967 llvm_unreachable("Do not know how to split this operator's operand!");
968
969 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
970 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
971 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
972 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
973 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
974 case ISD::STORE:
975 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
976 break;
977
978 case ISD::CTTZ:
979 case ISD::CTLZ:
980 case ISD::CTPOP:
981 case ISD::FP_EXTEND:
982 case ISD::FP_TO_SINT:
983 case ISD::FP_TO_UINT:
984 case ISD::SINT_TO_FP:
985 case ISD::UINT_TO_FP:
986 case ISD::FTRUNC:
987 case ISD::TRUNCATE:
988 case ISD::SIGN_EXTEND:
989 case ISD::ZERO_EXTEND:
990 case ISD::ANY_EXTEND:
991 Res = SplitVecOp_UnaryOp(N);
992 break;
993 }
994 }
995
996 // If the result is null, the sub-method took care of registering results etc.
997 if (!Res.getNode()) return false;
998
999 // If the result is N, the sub-method updated N in place. Tell the legalizer
1000 // core about this.
1001 if (Res.getNode() == N)
1002 return true;
1003
1004 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1005 "Invalid operand expansion");
1006
1007 ReplaceValueWith(SDValue(N, 0), Res);
1008 return false;
1009 }
1010
SplitVecOp_UnaryOp(SDNode * N)1011 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1012 // The result has a legal vector type, but the input needs splitting.
1013 EVT ResVT = N->getValueType(0);
1014 SDValue Lo, Hi;
1015 DebugLoc dl = N->getDebugLoc();
1016 GetSplitVector(N->getOperand(0), Lo, Hi);
1017 EVT InVT = Lo.getValueType();
1018
1019 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1020 InVT.getVectorNumElements());
1021
1022 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1023 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1024
1025 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1026 }
1027
SplitVecOp_BITCAST(SDNode * N)1028 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1029 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1030 // end up being split all the way down to individual components. Convert the
1031 // split pieces into integers and reassemble.
1032 SDValue Lo, Hi;
1033 GetSplitVector(N->getOperand(0), Lo, Hi);
1034 Lo = BitConvertToInteger(Lo);
1035 Hi = BitConvertToInteger(Hi);
1036
1037 if (TLI.isBigEndian())
1038 std::swap(Lo, Hi);
1039
1040 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1041 JoinIntegers(Lo, Hi));
1042 }
1043
SplitVecOp_EXTRACT_SUBVECTOR(SDNode * N)1044 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1045 // We know that the extracted result type is legal.
1046 EVT SubVT = N->getValueType(0);
1047 SDValue Idx = N->getOperand(1);
1048 DebugLoc dl = N->getDebugLoc();
1049 SDValue Lo, Hi;
1050 GetSplitVector(N->getOperand(0), Lo, Hi);
1051
1052 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1053 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1054
1055 if (IdxVal < LoElts) {
1056 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1057 "Extracted subvector crosses vector split!");
1058 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1059 } else {
1060 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1061 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1062 }
1063 }
1064
SplitVecOp_EXTRACT_VECTOR_ELT(SDNode * N)1065 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1066 SDValue Vec = N->getOperand(0);
1067 SDValue Idx = N->getOperand(1);
1068 EVT VecVT = Vec.getValueType();
1069
1070 if (isa<ConstantSDNode>(Idx)) {
1071 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1072 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1073
1074 SDValue Lo, Hi;
1075 GetSplitVector(Vec, Lo, Hi);
1076
1077 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1078
1079 if (IdxVal < LoElts)
1080 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1081 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1082 DAG.getConstant(IdxVal - LoElts,
1083 Idx.getValueType())), 0);
1084 }
1085
1086 // Store the vector to the stack.
1087 EVT EltVT = VecVT.getVectorElementType();
1088 DebugLoc dl = N->getDebugLoc();
1089 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1090 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1091 MachinePointerInfo(), false, false, 0);
1092
1093 // Load back the required element.
1094 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1095 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1096 MachinePointerInfo(), EltVT, false, false, 0);
1097 }
1098
SplitVecOp_STORE(StoreSDNode * N,unsigned OpNo)1099 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1100 assert(N->isUnindexed() && "Indexed store of vector?");
1101 assert(OpNo == 1 && "Can only split the stored value");
1102 DebugLoc DL = N->getDebugLoc();
1103
1104 bool isTruncating = N->isTruncatingStore();
1105 SDValue Ch = N->getChain();
1106 SDValue Ptr = N->getBasePtr();
1107 EVT MemoryVT = N->getMemoryVT();
1108 unsigned Alignment = N->getOriginalAlignment();
1109 bool isVol = N->isVolatile();
1110 bool isNT = N->isNonTemporal();
1111 SDValue Lo, Hi;
1112 GetSplitVector(N->getOperand(1), Lo, Hi);
1113
1114 EVT LoMemVT, HiMemVT;
1115 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1116
1117 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1118
1119 if (isTruncating)
1120 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1121 LoMemVT, isVol, isNT, Alignment);
1122 else
1123 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1124 isVol, isNT, Alignment);
1125
1126 // Increment the pointer to the other half.
1127 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1128 DAG.getIntPtrConstant(IncrementSize));
1129
1130 if (isTruncating)
1131 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1132 N->getPointerInfo().getWithOffset(IncrementSize),
1133 HiMemVT, isVol, isNT, Alignment);
1134 else
1135 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1136 N->getPointerInfo().getWithOffset(IncrementSize),
1137 isVol, isNT, Alignment);
1138
1139 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1140 }
1141
SplitVecOp_CONCAT_VECTORS(SDNode * N)1142 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1143 DebugLoc DL = N->getDebugLoc();
1144
1145 // The input operands all must have the same type, and we know the result the
1146 // result type is valid. Convert this to a buildvector which extracts all the
1147 // input elements.
1148 // TODO: If the input elements are power-two vectors, we could convert this to
1149 // a new CONCAT_VECTORS node with elements that are half-wide.
1150 SmallVector<SDValue, 32> Elts;
1151 EVT EltVT = N->getValueType(0).getVectorElementType();
1152 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1153 SDValue Op = N->getOperand(op);
1154 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1155 i != e; ++i) {
1156 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1157 Op, DAG.getIntPtrConstant(i)));
1158
1159 }
1160 }
1161
1162 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1163 &Elts[0], Elts.size());
1164 }
1165
SplitVecOp_FP_ROUND(SDNode * N)1166 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1167 // The result has a legal vector type, but the input needs splitting.
1168 EVT ResVT = N->getValueType(0);
1169 SDValue Lo, Hi;
1170 DebugLoc DL = N->getDebugLoc();
1171 GetSplitVector(N->getOperand(0), Lo, Hi);
1172 EVT InVT = Lo.getValueType();
1173
1174 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1175 InVT.getVectorNumElements());
1176
1177 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1178 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1179
1180 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1181 }
1182
1183
1184
1185 //===----------------------------------------------------------------------===//
1186 // Result Vector Widening
1187 //===----------------------------------------------------------------------===//
1188
WidenVectorResult(SDNode * N,unsigned ResNo)1189 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1190 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1191 N->dump(&DAG);
1192 dbgs() << "\n");
1193
1194 // See if the target wants to custom widen this node.
1195 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1196 return;
1197
1198 SDValue Res = SDValue();
1199 switch (N->getOpcode()) {
1200 default:
1201 #ifndef NDEBUG
1202 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1203 N->dump(&DAG);
1204 dbgs() << "\n";
1205 #endif
1206 llvm_unreachable("Do not know how to widen the result of this operator!");
1207
1208 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1209 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1210 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1211 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1212 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1213 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1214 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1215 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1216 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1217 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1218 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1219 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1220 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1221 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1222 case ISD::VECTOR_SHUFFLE:
1223 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1224 break;
1225 case ISD::VSETCC:
1226 Res = WidenVecRes_VSETCC(N);
1227 break;
1228
1229 case ISD::ADD:
1230 case ISD::AND:
1231 case ISD::BSWAP:
1232 case ISD::FADD:
1233 case ISD::FCOPYSIGN:
1234 case ISD::FDIV:
1235 case ISD::FMUL:
1236 case ISD::FPOW:
1237 case ISD::FREM:
1238 case ISD::FSUB:
1239 case ISD::MUL:
1240 case ISD::MULHS:
1241 case ISD::MULHU:
1242 case ISD::OR:
1243 case ISD::SDIV:
1244 case ISD::SREM:
1245 case ISD::UDIV:
1246 case ISD::UREM:
1247 case ISD::SUB:
1248 case ISD::XOR:
1249 Res = WidenVecRes_Binary(N);
1250 break;
1251
1252 case ISD::FPOWI:
1253 Res = WidenVecRes_POWI(N);
1254 break;
1255
1256 case ISD::SHL:
1257 case ISD::SRA:
1258 case ISD::SRL:
1259 Res = WidenVecRes_Shift(N);
1260 break;
1261
1262 case ISD::ANY_EXTEND:
1263 case ISD::FP_EXTEND:
1264 case ISD::FP_ROUND:
1265 case ISD::FP_TO_SINT:
1266 case ISD::FP_TO_UINT:
1267 case ISD::SIGN_EXTEND:
1268 case ISD::SINT_TO_FP:
1269 case ISD::TRUNCATE:
1270 case ISD::UINT_TO_FP:
1271 case ISD::ZERO_EXTEND:
1272 Res = WidenVecRes_Convert(N);
1273 break;
1274
1275 case ISD::CTLZ:
1276 case ISD::CTPOP:
1277 case ISD::CTTZ:
1278 case ISD::FABS:
1279 case ISD::FCEIL:
1280 case ISD::FCOS:
1281 case ISD::FEXP:
1282 case ISD::FEXP2:
1283 case ISD::FFLOOR:
1284 case ISD::FLOG:
1285 case ISD::FLOG10:
1286 case ISD::FLOG2:
1287 case ISD::FNEARBYINT:
1288 case ISD::FNEG:
1289 case ISD::FRINT:
1290 case ISD::FSIN:
1291 case ISD::FSQRT:
1292 case ISD::FTRUNC:
1293 Res = WidenVecRes_Unary(N);
1294 break;
1295 }
1296
1297 // If Res is null, the sub-method took care of registering the result.
1298 if (Res.getNode())
1299 SetWidenedVector(SDValue(N, ResNo), Res);
1300 }
1301
WidenVecRes_Binary(SDNode * N)1302 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1303 // Binary op widening.
1304 unsigned Opcode = N->getOpcode();
1305 DebugLoc dl = N->getDebugLoc();
1306 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1307 EVT WidenEltVT = WidenVT.getVectorElementType();
1308 EVT VT = WidenVT;
1309 unsigned NumElts = VT.getVectorNumElements();
1310 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1311 NumElts = NumElts / 2;
1312 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1313 }
1314
1315 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1316 // Operation doesn't trap so just widen as normal.
1317 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1318 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1319 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1320 }
1321
1322 // No legal vector version so unroll the vector operation and then widen.
1323 if (NumElts == 1)
1324 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1325
1326 // Since the operation can trap, apply operation on the original vector.
1327 EVT MaxVT = VT;
1328 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1329 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1330 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1331
1332 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1333 unsigned ConcatEnd = 0; // Current ConcatOps index.
1334 int Idx = 0; // Current Idx into input vectors.
1335
1336 // NumElts := greatest legal vector size (at most WidenVT)
1337 // while (orig. vector has unhandled elements) {
1338 // take munches of size NumElts from the beginning and add to ConcatOps
1339 // NumElts := next smaller supported vector size or 1
1340 // }
1341 while (CurNumElts != 0) {
1342 while (CurNumElts >= NumElts) {
1343 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1344 DAG.getIntPtrConstant(Idx));
1345 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1346 DAG.getIntPtrConstant(Idx));
1347 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1348 Idx += NumElts;
1349 CurNumElts -= NumElts;
1350 }
1351 do {
1352 NumElts = NumElts / 2;
1353 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1354 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1355
1356 if (NumElts == 1) {
1357 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1358 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1359 InOp1, DAG.getIntPtrConstant(Idx));
1360 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1361 InOp2, DAG.getIntPtrConstant(Idx));
1362 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1363 EOp1, EOp2);
1364 }
1365 CurNumElts = 0;
1366 }
1367 }
1368
1369 // Check to see if we have a single operation with the widen type.
1370 if (ConcatEnd == 1) {
1371 VT = ConcatOps[0].getValueType();
1372 if (VT == WidenVT)
1373 return ConcatOps[0];
1374 }
1375
1376 // while (Some element of ConcatOps is not of type MaxVT) {
1377 // From the end of ConcatOps, collect elements of the same type and put
1378 // them into an op of the next larger supported type
1379 // }
1380 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1381 Idx = ConcatEnd - 1;
1382 VT = ConcatOps[Idx--].getValueType();
1383 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1384 Idx--;
1385
1386 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1387 EVT NextVT;
1388 do {
1389 NextSize *= 2;
1390 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1391 } while (!TLI.isTypeLegal(NextVT));
1392
1393 if (!VT.isVector()) {
1394 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1395 SDValue VecOp = DAG.getUNDEF(NextVT);
1396 unsigned NumToInsert = ConcatEnd - Idx - 1;
1397 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1398 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1399 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1400 }
1401 ConcatOps[Idx+1] = VecOp;
1402 ConcatEnd = Idx + 2;
1403 } else {
1404 // Vector type, create a CONCAT_VECTORS of type NextVT
1405 SDValue undefVec = DAG.getUNDEF(VT);
1406 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1407 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1408 unsigned RealVals = ConcatEnd - Idx - 1;
1409 unsigned SubConcatEnd = 0;
1410 unsigned SubConcatIdx = Idx + 1;
1411 while (SubConcatEnd < RealVals)
1412 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1413 while (SubConcatEnd < OpsToConcat)
1414 SubConcatOps[SubConcatEnd++] = undefVec;
1415 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1416 NextVT, &SubConcatOps[0],
1417 OpsToConcat);
1418 ConcatEnd = SubConcatIdx + 1;
1419 }
1420 }
1421
1422 // Check to see if we have a single operation with the widen type.
1423 if (ConcatEnd == 1) {
1424 VT = ConcatOps[0].getValueType();
1425 if (VT == WidenVT)
1426 return ConcatOps[0];
1427 }
1428
1429 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1430 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1431 if (NumOps != ConcatEnd ) {
1432 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1433 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1434 ConcatOps[j] = UndefVal;
1435 }
1436 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1437 }
1438
WidenVecRes_Convert(SDNode * N)1439 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1440 SDValue InOp = N->getOperand(0);
1441 DebugLoc DL = N->getDebugLoc();
1442
1443 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1444 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1445
1446 EVT InVT = InOp.getValueType();
1447 EVT InEltVT = InVT.getVectorElementType();
1448 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1449
1450 unsigned Opcode = N->getOpcode();
1451 unsigned InVTNumElts = InVT.getVectorNumElements();
1452
1453 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1454 InOp = GetWidenedVector(N->getOperand(0));
1455 InVT = InOp.getValueType();
1456 InVTNumElts = InVT.getVectorNumElements();
1457 if (InVTNumElts == WidenNumElts) {
1458 if (N->getNumOperands() == 1)
1459 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1460 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1461 }
1462 }
1463
1464 if (TLI.isTypeLegal(InWidenVT)) {
1465 // Because the result and the input are different vector types, widening
1466 // the result could create a legal type but widening the input might make
1467 // it an illegal type that might lead to repeatedly splitting the input
1468 // and then widening it. To avoid this, we widen the input only if
1469 // it results in a legal type.
1470 if (WidenNumElts % InVTNumElts == 0) {
1471 // Widen the input and call convert on the widened input vector.
1472 unsigned NumConcat = WidenNumElts/InVTNumElts;
1473 SmallVector<SDValue, 16> Ops(NumConcat);
1474 Ops[0] = InOp;
1475 SDValue UndefVal = DAG.getUNDEF(InVT);
1476 for (unsigned i = 1; i != NumConcat; ++i)
1477 Ops[i] = UndefVal;
1478 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1479 &Ops[0], NumConcat);
1480 if (N->getNumOperands() == 1)
1481 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1482 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1483 }
1484
1485 if (InVTNumElts % WidenNumElts == 0) {
1486 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1487 InOp, DAG.getIntPtrConstant(0));
1488 // Extract the input and convert the shorten input vector.
1489 if (N->getNumOperands() == 1)
1490 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1491 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1492 }
1493 }
1494
1495 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1496 SmallVector<SDValue, 16> Ops(WidenNumElts);
1497 EVT EltVT = WidenVT.getVectorElementType();
1498 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1499 unsigned i;
1500 for (i=0; i < MinElts; ++i) {
1501 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1502 DAG.getIntPtrConstant(i));
1503 if (N->getNumOperands() == 1)
1504 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1505 else
1506 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1507 }
1508
1509 SDValue UndefVal = DAG.getUNDEF(EltVT);
1510 for (; i < WidenNumElts; ++i)
1511 Ops[i] = UndefVal;
1512
1513 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1514 }
1515
WidenVecRes_POWI(SDNode * N)1516 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1517 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1518 SDValue InOp = GetWidenedVector(N->getOperand(0));
1519 SDValue ShOp = N->getOperand(1);
1520 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1521 }
1522
WidenVecRes_Shift(SDNode * N)1523 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1524 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1525 SDValue InOp = GetWidenedVector(N->getOperand(0));
1526 SDValue ShOp = N->getOperand(1);
1527
1528 EVT ShVT = ShOp.getValueType();
1529 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1530 ShOp = GetWidenedVector(ShOp);
1531 ShVT = ShOp.getValueType();
1532 }
1533 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1534 ShVT.getVectorElementType(),
1535 WidenVT.getVectorNumElements());
1536 if (ShVT != ShWidenVT)
1537 ShOp = ModifyToType(ShOp, ShWidenVT);
1538
1539 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1540 }
1541
WidenVecRes_Unary(SDNode * N)1542 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1543 // Unary op widening.
1544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1545 SDValue InOp = GetWidenedVector(N->getOperand(0));
1546 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1547 }
1548
WidenVecRes_InregOp(SDNode * N)1549 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1550 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1551 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1552 cast<VTSDNode>(N->getOperand(1))->getVT()
1553 .getVectorElementType(),
1554 WidenVT.getVectorNumElements());
1555 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1556 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1557 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1558 }
1559
WidenVecRes_BITCAST(SDNode * N)1560 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1561 SDValue InOp = N->getOperand(0);
1562 EVT InVT = InOp.getValueType();
1563 EVT VT = N->getValueType(0);
1564 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1565 DebugLoc dl = N->getDebugLoc();
1566
1567 switch (getTypeAction(InVT)) {
1568 default:
1569 assert(false && "Unknown type action!");
1570 break;
1571 case TargetLowering::TypeLegal:
1572 break;
1573 case TargetLowering::TypePromoteInteger:
1574 // If the InOp is promoted to the same size, convert it. Otherwise,
1575 // fall out of the switch and widen the promoted input.
1576 InOp = GetPromotedInteger(InOp);
1577 InVT = InOp.getValueType();
1578 if (WidenVT.bitsEq(InVT))
1579 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1580 break;
1581 case TargetLowering::TypeSoftenFloat:
1582 case TargetLowering::TypeExpandInteger:
1583 case TargetLowering::TypeExpandFloat:
1584 case TargetLowering::TypeScalarizeVector:
1585 case TargetLowering::TypeSplitVector:
1586 break;
1587 case TargetLowering::TypeWidenVector:
1588 // If the InOp is widened to the same size, convert it. Otherwise, fall
1589 // out of the switch and widen the widened input.
1590 InOp = GetWidenedVector(InOp);
1591 InVT = InOp.getValueType();
1592 if (WidenVT.bitsEq(InVT))
1593 // The input widens to the same size. Convert to the widen value.
1594 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1595 break;
1596 }
1597
1598 unsigned WidenSize = WidenVT.getSizeInBits();
1599 unsigned InSize = InVT.getSizeInBits();
1600 // x86mmx is not an acceptable vector element type, so don't try.
1601 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1602 // Determine new input vector type. The new input vector type will use
1603 // the same element type (if its a vector) or use the input type as a
1604 // vector. It is the same size as the type to widen to.
1605 EVT NewInVT;
1606 unsigned NewNumElts = WidenSize / InSize;
1607 if (InVT.isVector()) {
1608 EVT InEltVT = InVT.getVectorElementType();
1609 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1610 WidenSize / InEltVT.getSizeInBits());
1611 } else {
1612 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1613 }
1614
1615 if (TLI.isTypeLegal(NewInVT)) {
1616 // Because the result and the input are different vector types, widening
1617 // the result could create a legal type but widening the input might make
1618 // it an illegal type that might lead to repeatedly splitting the input
1619 // and then widening it. To avoid this, we widen the input only if
1620 // it results in a legal type.
1621 SmallVector<SDValue, 16> Ops(NewNumElts);
1622 SDValue UndefVal = DAG.getUNDEF(InVT);
1623 Ops[0] = InOp;
1624 for (unsigned i = 1; i < NewNumElts; ++i)
1625 Ops[i] = UndefVal;
1626
1627 SDValue NewVec;
1628 if (InVT.isVector())
1629 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1630 NewInVT, &Ops[0], NewNumElts);
1631 else
1632 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1633 NewInVT, &Ops[0], NewNumElts);
1634 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1635 }
1636 }
1637
1638 return CreateStackStoreLoad(InOp, WidenVT);
1639 }
1640
WidenVecRes_BUILD_VECTOR(SDNode * N)1641 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1642 DebugLoc dl = N->getDebugLoc();
1643 // Build a vector with undefined for the new nodes.
1644 EVT VT = N->getValueType(0);
1645 EVT EltVT = VT.getVectorElementType();
1646 unsigned NumElts = VT.getVectorNumElements();
1647
1648 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1649 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1650
1651 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1652 NewOps.reserve(WidenNumElts);
1653 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1654 NewOps.push_back(DAG.getUNDEF(EltVT));
1655
1656 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1657 }
1658
WidenVecRes_CONCAT_VECTORS(SDNode * N)1659 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1660 EVT InVT = N->getOperand(0).getValueType();
1661 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1662 DebugLoc dl = N->getDebugLoc();
1663 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1664 unsigned NumOperands = N->getNumOperands();
1665
1666 bool InputWidened = false; // Indicates we need to widen the input.
1667 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1668 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1669 // Add undef vectors to widen to correct length.
1670 unsigned NumConcat = WidenVT.getVectorNumElements() /
1671 InVT.getVectorNumElements();
1672 SDValue UndefVal = DAG.getUNDEF(InVT);
1673 SmallVector<SDValue, 16> Ops(NumConcat);
1674 for (unsigned i=0; i < NumOperands; ++i)
1675 Ops[i] = N->getOperand(i);
1676 for (unsigned i = NumOperands; i != NumConcat; ++i)
1677 Ops[i] = UndefVal;
1678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1679 }
1680 } else {
1681 InputWidened = true;
1682 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1683 // The inputs and the result are widen to the same value.
1684 unsigned i;
1685 for (i=1; i < NumOperands; ++i)
1686 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1687 break;
1688
1689 if (i > NumOperands)
1690 // Everything but the first operand is an UNDEF so just return the
1691 // widened first operand.
1692 return GetWidenedVector(N->getOperand(0));
1693
1694 if (NumOperands == 2) {
1695 // Replace concat of two operands with a shuffle.
1696 SmallVector<int, 16> MaskOps(WidenNumElts);
1697 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1698 MaskOps[i] = i;
1699 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1700 }
1701 return DAG.getVectorShuffle(WidenVT, dl,
1702 GetWidenedVector(N->getOperand(0)),
1703 GetWidenedVector(N->getOperand(1)),
1704 &MaskOps[0]);
1705 }
1706 }
1707 }
1708
1709 // Fall back to use extracts and build vector.
1710 EVT EltVT = WidenVT.getVectorElementType();
1711 unsigned NumInElts = InVT.getVectorNumElements();
1712 SmallVector<SDValue, 16> Ops(WidenNumElts);
1713 unsigned Idx = 0;
1714 for (unsigned i=0; i < NumOperands; ++i) {
1715 SDValue InOp = N->getOperand(i);
1716 if (InputWidened)
1717 InOp = GetWidenedVector(InOp);
1718 for (unsigned j=0; j < NumInElts; ++j)
1719 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1720 DAG.getIntPtrConstant(j));
1721 }
1722 SDValue UndefVal = DAG.getUNDEF(EltVT);
1723 for (; Idx < WidenNumElts; ++Idx)
1724 Ops[Idx] = UndefVal;
1725 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1726 }
1727
WidenVecRes_CONVERT_RNDSAT(SDNode * N)1728 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1729 DebugLoc dl = N->getDebugLoc();
1730 SDValue InOp = N->getOperand(0);
1731 SDValue RndOp = N->getOperand(3);
1732 SDValue SatOp = N->getOperand(4);
1733
1734 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1735 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1736
1737 EVT InVT = InOp.getValueType();
1738 EVT InEltVT = InVT.getVectorElementType();
1739 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1740
1741 SDValue DTyOp = DAG.getValueType(WidenVT);
1742 SDValue STyOp = DAG.getValueType(InWidenVT);
1743 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1744
1745 unsigned InVTNumElts = InVT.getVectorNumElements();
1746 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1747 InOp = GetWidenedVector(InOp);
1748 InVT = InOp.getValueType();
1749 InVTNumElts = InVT.getVectorNumElements();
1750 if (InVTNumElts == WidenNumElts)
1751 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1752 SatOp, CvtCode);
1753 }
1754
1755 if (TLI.isTypeLegal(InWidenVT)) {
1756 // Because the result and the input are different vector types, widening
1757 // the result could create a legal type but widening the input might make
1758 // it an illegal type that might lead to repeatedly splitting the input
1759 // and then widening it. To avoid this, we widen the input only if
1760 // it results in a legal type.
1761 if (WidenNumElts % InVTNumElts == 0) {
1762 // Widen the input and call convert on the widened input vector.
1763 unsigned NumConcat = WidenNumElts/InVTNumElts;
1764 SmallVector<SDValue, 16> Ops(NumConcat);
1765 Ops[0] = InOp;
1766 SDValue UndefVal = DAG.getUNDEF(InVT);
1767 for (unsigned i = 1; i != NumConcat; ++i)
1768 Ops[i] = UndefVal;
1769
1770 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1771 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1772 SatOp, CvtCode);
1773 }
1774
1775 if (InVTNumElts % WidenNumElts == 0) {
1776 // Extract the input and convert the shorten input vector.
1777 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1778 DAG.getIntPtrConstant(0));
1779 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1780 SatOp, CvtCode);
1781 }
1782 }
1783
1784 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1785 SmallVector<SDValue, 16> Ops(WidenNumElts);
1786 EVT EltVT = WidenVT.getVectorElementType();
1787 DTyOp = DAG.getValueType(EltVT);
1788 STyOp = DAG.getValueType(InEltVT);
1789
1790 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1791 unsigned i;
1792 for (i=0; i < MinElts; ++i) {
1793 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1794 DAG.getIntPtrConstant(i));
1795 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1796 SatOp, CvtCode);
1797 }
1798
1799 SDValue UndefVal = DAG.getUNDEF(EltVT);
1800 for (; i < WidenNumElts; ++i)
1801 Ops[i] = UndefVal;
1802
1803 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1804 }
1805
WidenVecRes_EXTRACT_SUBVECTOR(SDNode * N)1806 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1807 EVT VT = N->getValueType(0);
1808 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1809 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1810 SDValue InOp = N->getOperand(0);
1811 SDValue Idx = N->getOperand(1);
1812 DebugLoc dl = N->getDebugLoc();
1813
1814 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1815 InOp = GetWidenedVector(InOp);
1816
1817 EVT InVT = InOp.getValueType();
1818
1819 // Check if we can just return the input vector after widening.
1820 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1821 if (IdxVal == 0 && InVT == WidenVT)
1822 return InOp;
1823
1824 // Check if we can extract from the vector.
1825 unsigned InNumElts = InVT.getVectorNumElements();
1826 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1827 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1828
1829 // We could try widening the input to the right length but for now, extract
1830 // the original elements, fill the rest with undefs and build a vector.
1831 SmallVector<SDValue, 16> Ops(WidenNumElts);
1832 EVT EltVT = VT.getVectorElementType();
1833 unsigned NumElts = VT.getVectorNumElements();
1834 unsigned i;
1835 for (i=0; i < NumElts; ++i)
1836 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1837 DAG.getIntPtrConstant(IdxVal+i));
1838
1839 SDValue UndefVal = DAG.getUNDEF(EltVT);
1840 for (; i < WidenNumElts; ++i)
1841 Ops[i] = UndefVal;
1842 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1843 }
1844
WidenVecRes_INSERT_VECTOR_ELT(SDNode * N)1845 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1846 SDValue InOp = GetWidenedVector(N->getOperand(0));
1847 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1848 InOp.getValueType(), InOp,
1849 N->getOperand(1), N->getOperand(2));
1850 }
1851
WidenVecRes_LOAD(SDNode * N)1852 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1853 LoadSDNode *LD = cast<LoadSDNode>(N);
1854 ISD::LoadExtType ExtType = LD->getExtensionType();
1855
1856 SDValue Result;
1857 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1858 if (ExtType != ISD::NON_EXTLOAD)
1859 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1860 else
1861 Result = GenWidenVectorLoads(LdChain, LD);
1862
1863 // If we generate a single load, we can use that for the chain. Otherwise,
1864 // build a factor node to remember the multiple loads are independent and
1865 // chain to that.
1866 SDValue NewChain;
1867 if (LdChain.size() == 1)
1868 NewChain = LdChain[0];
1869 else
1870 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1871 &LdChain[0], LdChain.size());
1872
1873 // Modified the chain - switch anything that used the old chain to use
1874 // the new one.
1875 ReplaceValueWith(SDValue(N, 1), NewChain);
1876
1877 return Result;
1878 }
1879
WidenVecRes_SCALAR_TO_VECTOR(SDNode * N)1880 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1881 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1882 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1883 WidenVT, N->getOperand(0));
1884 }
1885
WidenVecRes_SELECT(SDNode * N)1886 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1887 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1888 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1889
1890 SDValue Cond1 = N->getOperand(0);
1891 EVT CondVT = Cond1.getValueType();
1892 if (CondVT.isVector()) {
1893 EVT CondEltVT = CondVT.getVectorElementType();
1894 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1895 CondEltVT, WidenNumElts);
1896 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
1897 Cond1 = GetWidenedVector(Cond1);
1898
1899 if (Cond1.getValueType() != CondWidenVT)
1900 Cond1 = ModifyToType(Cond1, CondWidenVT);
1901 }
1902
1903 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1904 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1905 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1906 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1907 WidenVT, Cond1, InOp1, InOp2);
1908 }
1909
WidenVecRes_SELECT_CC(SDNode * N)1910 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1911 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1912 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1913 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1914 InOp1.getValueType(), N->getOperand(0),
1915 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1916 }
1917
WidenVecRes_SETCC(SDNode * N)1918 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1920 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1921 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1922 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1923 InOp1, InOp2, N->getOperand(2));
1924 }
1925
WidenVecRes_UNDEF(SDNode * N)1926 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1927 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1928 return DAG.getUNDEF(WidenVT);
1929 }
1930
WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode * N)1931 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1932 EVT VT = N->getValueType(0);
1933 DebugLoc dl = N->getDebugLoc();
1934
1935 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1936 unsigned NumElts = VT.getVectorNumElements();
1937 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1938
1939 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1940 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1941
1942 // Adjust mask based on new input vector length.
1943 SmallVector<int, 16> NewMask;
1944 for (unsigned i = 0; i != NumElts; ++i) {
1945 int Idx = N->getMaskElt(i);
1946 if (Idx < (int)NumElts)
1947 NewMask.push_back(Idx);
1948 else
1949 NewMask.push_back(Idx - NumElts + WidenNumElts);
1950 }
1951 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1952 NewMask.push_back(-1);
1953 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1954 }
1955
WidenVecRes_VSETCC(SDNode * N)1956 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1957 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1958 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1959
1960 SDValue InOp1 = N->getOperand(0);
1961 EVT InVT = InOp1.getValueType();
1962 assert(InVT.isVector() && "can not widen non vector type");
1963 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
1964 InVT.getVectorElementType(), WidenNumElts);
1965 InOp1 = GetWidenedVector(InOp1);
1966 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1967
1968 // Assume that the input and output will be widen appropriately. If not,
1969 // we will have to unroll it at some point.
1970 assert(InOp1.getValueType() == WidenInVT &&
1971 InOp2.getValueType() == WidenInVT &&
1972 "Input not widened to expected type!");
1973 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1974 WidenVT, InOp1, InOp2, N->getOperand(2));
1975 }
1976
1977
1978 //===----------------------------------------------------------------------===//
1979 // Widen Vector Operand
1980 //===----------------------------------------------------------------------===//
WidenVectorOperand(SDNode * N,unsigned ResNo)1981 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1982 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
1983 N->dump(&DAG);
1984 dbgs() << "\n");
1985 SDValue Res = SDValue();
1986
1987 switch (N->getOpcode()) {
1988 default:
1989 #ifndef NDEBUG
1990 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
1991 N->dump(&DAG);
1992 dbgs() << "\n";
1993 #endif
1994 llvm_unreachable("Do not know how to widen this operator's operand!");
1995
1996 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
1997 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1998 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
1999 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2000 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2001
2002 case ISD::FP_EXTEND:
2003 case ISD::FP_TO_SINT:
2004 case ISD::FP_TO_UINT:
2005 case ISD::SINT_TO_FP:
2006 case ISD::UINT_TO_FP:
2007 case ISD::TRUNCATE:
2008 case ISD::SIGN_EXTEND:
2009 case ISD::ZERO_EXTEND:
2010 case ISD::ANY_EXTEND:
2011 Res = WidenVecOp_Convert(N);
2012 break;
2013 }
2014
2015 // If Res is null, the sub-method took care of registering the result.
2016 if (!Res.getNode()) return false;
2017
2018 // If the result is N, the sub-method updated N in place. Tell the legalizer
2019 // core about this.
2020 if (Res.getNode() == N)
2021 return true;
2022
2023
2024 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2025 "Invalid operand expansion");
2026
2027 ReplaceValueWith(SDValue(N, 0), Res);
2028 return false;
2029 }
2030
WidenVecOp_Convert(SDNode * N)2031 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2032 // Since the result is legal and the input is illegal, it is unlikely
2033 // that we can fix the input to a legal type so unroll the convert
2034 // into some scalar code and create a nasty build vector.
2035 EVT VT = N->getValueType(0);
2036 EVT EltVT = VT.getVectorElementType();
2037 DebugLoc dl = N->getDebugLoc();
2038 unsigned NumElts = VT.getVectorNumElements();
2039 SDValue InOp = N->getOperand(0);
2040 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2041 InOp = GetWidenedVector(InOp);
2042 EVT InVT = InOp.getValueType();
2043 EVT InEltVT = InVT.getVectorElementType();
2044
2045 unsigned Opcode = N->getOpcode();
2046 SmallVector<SDValue, 16> Ops(NumElts);
2047 for (unsigned i=0; i < NumElts; ++i)
2048 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2049 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2050 DAG.getIntPtrConstant(i)));
2051
2052 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2053 }
2054
WidenVecOp_BITCAST(SDNode * N)2055 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2056 EVT VT = N->getValueType(0);
2057 SDValue InOp = GetWidenedVector(N->getOperand(0));
2058 EVT InWidenVT = InOp.getValueType();
2059 DebugLoc dl = N->getDebugLoc();
2060
2061 // Check if we can convert between two legal vector types and extract.
2062 unsigned InWidenSize = InWidenVT.getSizeInBits();
2063 unsigned Size = VT.getSizeInBits();
2064 // x86mmx is not an acceptable vector element type, so don't try.
2065 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2066 unsigned NewNumElts = InWidenSize / Size;
2067 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2068 if (TLI.isTypeLegal(NewVT)) {
2069 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2070 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2071 DAG.getIntPtrConstant(0));
2072 }
2073 }
2074
2075 return CreateStackStoreLoad(InOp, VT);
2076 }
2077
WidenVecOp_CONCAT_VECTORS(SDNode * N)2078 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2079 // If the input vector is not legal, it is likely that we will not find a
2080 // legal vector of the same size. Replace the concatenate vector with a
2081 // nasty build vector.
2082 EVT VT = N->getValueType(0);
2083 EVT EltVT = VT.getVectorElementType();
2084 DebugLoc dl = N->getDebugLoc();
2085 unsigned NumElts = VT.getVectorNumElements();
2086 SmallVector<SDValue, 16> Ops(NumElts);
2087
2088 EVT InVT = N->getOperand(0).getValueType();
2089 unsigned NumInElts = InVT.getVectorNumElements();
2090
2091 unsigned Idx = 0;
2092 unsigned NumOperands = N->getNumOperands();
2093 for (unsigned i=0; i < NumOperands; ++i) {
2094 SDValue InOp = N->getOperand(i);
2095 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2096 InOp = GetWidenedVector(InOp);
2097 for (unsigned j=0; j < NumInElts; ++j)
2098 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2099 DAG.getIntPtrConstant(j));
2100 }
2101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2102 }
2103
WidenVecOp_EXTRACT_SUBVECTOR(SDNode * N)2104 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2105 SDValue InOp = GetWidenedVector(N->getOperand(0));
2106 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2107 N->getValueType(0), InOp, N->getOperand(1));
2108 }
2109
WidenVecOp_EXTRACT_VECTOR_ELT(SDNode * N)2110 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2111 SDValue InOp = GetWidenedVector(N->getOperand(0));
2112 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2113 N->getValueType(0), InOp, N->getOperand(1));
2114 }
2115
WidenVecOp_STORE(SDNode * N)2116 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2117 // We have to widen the value but we want only to store the original
2118 // vector type.
2119 StoreSDNode *ST = cast<StoreSDNode>(N);
2120
2121 SmallVector<SDValue, 16> StChain;
2122 if (ST->isTruncatingStore())
2123 GenWidenVectorTruncStores(StChain, ST);
2124 else
2125 GenWidenVectorStores(StChain, ST);
2126
2127 if (StChain.size() == 1)
2128 return StChain[0];
2129 else
2130 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2131 MVT::Other,&StChain[0],StChain.size());
2132 }
2133
2134 //===----------------------------------------------------------------------===//
2135 // Vector Widening Utilities
2136 //===----------------------------------------------------------------------===//
2137
2138 // Utility function to find the type to chop up a widen vector for load/store
2139 // TLI: Target lowering used to determine legal types.
2140 // Width: Width left need to load/store.
2141 // WidenVT: The widen vector type to load to/store from
2142 // Align: If 0, don't allow use of a wider type
2143 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2144
FindMemType(SelectionDAG & DAG,const TargetLowering & TLI,unsigned Width,EVT WidenVT,unsigned Align=0,unsigned WidenEx=0)2145 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2146 unsigned Width, EVT WidenVT,
2147 unsigned Align = 0, unsigned WidenEx = 0) {
2148 EVT WidenEltVT = WidenVT.getVectorElementType();
2149 unsigned WidenWidth = WidenVT.getSizeInBits();
2150 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2151 unsigned AlignInBits = Align*8;
2152
2153 // If we have one element to load/store, return it.
2154 EVT RetVT = WidenEltVT;
2155 if (Width == WidenEltWidth)
2156 return RetVT;
2157
2158 // See if there is larger legal integer than the element type to load/store
2159 unsigned VT;
2160 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2161 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2162 EVT MemVT((MVT::SimpleValueType) VT);
2163 unsigned MemVTWidth = MemVT.getSizeInBits();
2164 if (MemVT.getSizeInBits() <= WidenEltWidth)
2165 break;
2166 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2167 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2168 (MemVTWidth <= Width ||
2169 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2170 RetVT = MemVT;
2171 break;
2172 }
2173 }
2174
2175 // See if there is a larger vector type to load/store that has the same vector
2176 // element type and is evenly divisible with the WidenVT.
2177 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2178 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2179 EVT MemVT = (MVT::SimpleValueType) VT;
2180 unsigned MemVTWidth = MemVT.getSizeInBits();
2181 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2182 (WidenWidth % MemVTWidth) == 0 &&
2183 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2184 (MemVTWidth <= Width ||
2185 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2186 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2187 return MemVT;
2188 }
2189 }
2190
2191 return RetVT;
2192 }
2193
2194 // Builds a vector type from scalar loads
2195 // VecTy: Resulting Vector type
2196 // LDOps: Load operators to build a vector type
2197 // [Start,End) the list of loads to use.
BuildVectorFromScalar(SelectionDAG & DAG,EVT VecTy,SmallVector<SDValue,16> & LdOps,unsigned Start,unsigned End)2198 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2199 SmallVector<SDValue, 16>& LdOps,
2200 unsigned Start, unsigned End) {
2201 DebugLoc dl = LdOps[Start].getDebugLoc();
2202 EVT LdTy = LdOps[Start].getValueType();
2203 unsigned Width = VecTy.getSizeInBits();
2204 unsigned NumElts = Width / LdTy.getSizeInBits();
2205 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2206
2207 unsigned Idx = 1;
2208 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2209
2210 for (unsigned i = Start + 1; i != End; ++i) {
2211 EVT NewLdTy = LdOps[i].getValueType();
2212 if (NewLdTy != LdTy) {
2213 NumElts = Width / NewLdTy.getSizeInBits();
2214 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2215 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2216 // Readjust position and vector position based on new load type
2217 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2218 LdTy = NewLdTy;
2219 }
2220 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2221 DAG.getIntPtrConstant(Idx++));
2222 }
2223 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2224 }
2225
GenWidenVectorLoads(SmallVector<SDValue,16> & LdChain,LoadSDNode * LD)2226 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2227 LoadSDNode *LD) {
2228 // The strategy assumes that we can efficiently load powers of two widths.
2229 // The routines chops the vector into the largest vector loads with the same
2230 // element type or scalar loads and then recombines it to the widen vector
2231 // type.
2232 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2233 unsigned WidenWidth = WidenVT.getSizeInBits();
2234 EVT LdVT = LD->getMemoryVT();
2235 DebugLoc dl = LD->getDebugLoc();
2236 assert(LdVT.isVector() && WidenVT.isVector());
2237 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2238
2239 // Load information
2240 SDValue Chain = LD->getChain();
2241 SDValue BasePtr = LD->getBasePtr();
2242 unsigned Align = LD->getAlignment();
2243 bool isVolatile = LD->isVolatile();
2244 bool isNonTemporal = LD->isNonTemporal();
2245
2246 int LdWidth = LdVT.getSizeInBits();
2247 int WidthDiff = WidenWidth - LdWidth; // Difference
2248 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2249
2250 // Find the vector type that can load from.
2251 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2252 int NewVTWidth = NewVT.getSizeInBits();
2253 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2254 isVolatile, isNonTemporal, Align);
2255 LdChain.push_back(LdOp.getValue(1));
2256
2257 // Check if we can load the element with one instruction
2258 if (LdWidth <= NewVTWidth) {
2259 if (!NewVT.isVector()) {
2260 unsigned NumElts = WidenWidth / NewVTWidth;
2261 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2262 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2263 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2264 }
2265 if (NewVT == WidenVT)
2266 return LdOp;
2267
2268 assert(WidenWidth % NewVTWidth == 0);
2269 unsigned NumConcat = WidenWidth / NewVTWidth;
2270 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2271 SDValue UndefVal = DAG.getUNDEF(NewVT);
2272 ConcatOps[0] = LdOp;
2273 for (unsigned i = 1; i != NumConcat; ++i)
2274 ConcatOps[i] = UndefVal;
2275 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2276 NumConcat);
2277 }
2278
2279 // Load vector by using multiple loads from largest vector to scalar
2280 SmallVector<SDValue, 16> LdOps;
2281 LdOps.push_back(LdOp);
2282
2283 LdWidth -= NewVTWidth;
2284 unsigned Offset = 0;
2285
2286 while (LdWidth > 0) {
2287 unsigned Increment = NewVTWidth / 8;
2288 Offset += Increment;
2289 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2290 DAG.getIntPtrConstant(Increment));
2291
2292 if (LdWidth < NewVTWidth) {
2293 // Our current type we are using is too large, find a better size
2294 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2295 NewVTWidth = NewVT.getSizeInBits();
2296 }
2297
2298 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2299 LD->getPointerInfo().getWithOffset(Offset),
2300 isVolatile,
2301 isNonTemporal, MinAlign(Align, Increment));
2302 LdChain.push_back(LdOp.getValue(1));
2303 LdOps.push_back(LdOp);
2304
2305 LdWidth -= NewVTWidth;
2306 }
2307
2308 // Build the vector from the loads operations
2309 unsigned End = LdOps.size();
2310 if (!LdOps[0].getValueType().isVector())
2311 // All the loads are scalar loads.
2312 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2313
2314 // If the load contains vectors, build the vector using concat vector.
2315 // All of the vectors used to loads are power of 2 and the scalars load
2316 // can be combined to make a power of 2 vector.
2317 SmallVector<SDValue, 16> ConcatOps(End);
2318 int i = End - 1;
2319 int Idx = End;
2320 EVT LdTy = LdOps[i].getValueType();
2321 // First combine the scalar loads to a vector
2322 if (!LdTy.isVector()) {
2323 for (--i; i >= 0; --i) {
2324 LdTy = LdOps[i].getValueType();
2325 if (LdTy.isVector())
2326 break;
2327 }
2328 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2329 }
2330 ConcatOps[--Idx] = LdOps[i];
2331 for (--i; i >= 0; --i) {
2332 EVT NewLdTy = LdOps[i].getValueType();
2333 if (NewLdTy != LdTy) {
2334 // Create a larger vector
2335 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2336 &ConcatOps[Idx], End - Idx);
2337 Idx = End - 1;
2338 LdTy = NewLdTy;
2339 }
2340 ConcatOps[--Idx] = LdOps[i];
2341 }
2342
2343 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2344 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2345 &ConcatOps[Idx], End - Idx);
2346
2347 // We need to fill the rest with undefs to build the vector
2348 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2349 SmallVector<SDValue, 16> WidenOps(NumOps);
2350 SDValue UndefVal = DAG.getUNDEF(LdTy);
2351 {
2352 unsigned i = 0;
2353 for (; i != End-Idx; ++i)
2354 WidenOps[i] = ConcatOps[Idx+i];
2355 for (; i != NumOps; ++i)
2356 WidenOps[i] = UndefVal;
2357 }
2358 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2359 }
2360
2361 SDValue
GenWidenVectorExtLoads(SmallVector<SDValue,16> & LdChain,LoadSDNode * LD,ISD::LoadExtType ExtType)2362 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2363 LoadSDNode * LD,
2364 ISD::LoadExtType ExtType) {
2365 // For extension loads, it may not be more efficient to chop up the vector
2366 // and then extended it. Instead, we unroll the load and build a new vector.
2367 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2368 EVT LdVT = LD->getMemoryVT();
2369 DebugLoc dl = LD->getDebugLoc();
2370 assert(LdVT.isVector() && WidenVT.isVector());
2371
2372 // Load information
2373 SDValue Chain = LD->getChain();
2374 SDValue BasePtr = LD->getBasePtr();
2375 unsigned Align = LD->getAlignment();
2376 bool isVolatile = LD->isVolatile();
2377 bool isNonTemporal = LD->isNonTemporal();
2378
2379 EVT EltVT = WidenVT.getVectorElementType();
2380 EVT LdEltVT = LdVT.getVectorElementType();
2381 unsigned NumElts = LdVT.getVectorNumElements();
2382
2383 // Load each element and widen
2384 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2385 SmallVector<SDValue, 16> Ops(WidenNumElts);
2386 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2387 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2388 LD->getPointerInfo(),
2389 LdEltVT, isVolatile, isNonTemporal, Align);
2390 LdChain.push_back(Ops[0].getValue(1));
2391 unsigned i = 0, Offset = Increment;
2392 for (i=1; i < NumElts; ++i, Offset += Increment) {
2393 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2394 BasePtr, DAG.getIntPtrConstant(Offset));
2395 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2396 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2397 isVolatile, isNonTemporal, Align);
2398 LdChain.push_back(Ops[i].getValue(1));
2399 }
2400
2401 // Fill the rest with undefs
2402 SDValue UndefVal = DAG.getUNDEF(EltVT);
2403 for (; i != WidenNumElts; ++i)
2404 Ops[i] = UndefVal;
2405
2406 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2407 }
2408
2409
GenWidenVectorStores(SmallVector<SDValue,16> & StChain,StoreSDNode * ST)2410 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2411 StoreSDNode *ST) {
2412 // The strategy assumes that we can efficiently store powers of two widths.
2413 // The routines chops the vector into the largest vector stores with the same
2414 // element type or scalar stores.
2415 SDValue Chain = ST->getChain();
2416 SDValue BasePtr = ST->getBasePtr();
2417 unsigned Align = ST->getAlignment();
2418 bool isVolatile = ST->isVolatile();
2419 bool isNonTemporal = ST->isNonTemporal();
2420 SDValue ValOp = GetWidenedVector(ST->getValue());
2421 DebugLoc dl = ST->getDebugLoc();
2422
2423 EVT StVT = ST->getMemoryVT();
2424 unsigned StWidth = StVT.getSizeInBits();
2425 EVT ValVT = ValOp.getValueType();
2426 unsigned ValWidth = ValVT.getSizeInBits();
2427 EVT ValEltVT = ValVT.getVectorElementType();
2428 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2429 assert(StVT.getVectorElementType() == ValEltVT);
2430
2431 int Idx = 0; // current index to store
2432 unsigned Offset = 0; // offset from base to store
2433 while (StWidth != 0) {
2434 // Find the largest vector type we can store with
2435 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2436 unsigned NewVTWidth = NewVT.getSizeInBits();
2437 unsigned Increment = NewVTWidth / 8;
2438 if (NewVT.isVector()) {
2439 unsigned NumVTElts = NewVT.getVectorNumElements();
2440 do {
2441 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2442 DAG.getIntPtrConstant(Idx));
2443 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2444 ST->getPointerInfo().getWithOffset(Offset),
2445 isVolatile, isNonTemporal,
2446 MinAlign(Align, Offset)));
2447 StWidth -= NewVTWidth;
2448 Offset += Increment;
2449 Idx += NumVTElts;
2450 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2451 DAG.getIntPtrConstant(Increment));
2452 } while (StWidth != 0 && StWidth >= NewVTWidth);
2453 } else {
2454 // Cast the vector to the scalar type we can store
2455 unsigned NumElts = ValWidth / NewVTWidth;
2456 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2457 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2458 // Readjust index position based on new vector type
2459 Idx = Idx * ValEltWidth / NewVTWidth;
2460 do {
2461 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2462 DAG.getIntPtrConstant(Idx++));
2463 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2464 ST->getPointerInfo().getWithOffset(Offset),
2465 isVolatile, isNonTemporal,
2466 MinAlign(Align, Offset)));
2467 StWidth -= NewVTWidth;
2468 Offset += Increment;
2469 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2470 DAG.getIntPtrConstant(Increment));
2471 } while (StWidth != 0 && StWidth >= NewVTWidth);
2472 // Restore index back to be relative to the original widen element type
2473 Idx = Idx * NewVTWidth / ValEltWidth;
2474 }
2475 }
2476 }
2477
2478 void
GenWidenVectorTruncStores(SmallVector<SDValue,16> & StChain,StoreSDNode * ST)2479 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2480 StoreSDNode *ST) {
2481 // For extension loads, it may not be more efficient to truncate the vector
2482 // and then store it. Instead, we extract each element and then store it.
2483 SDValue Chain = ST->getChain();
2484 SDValue BasePtr = ST->getBasePtr();
2485 unsigned Align = ST->getAlignment();
2486 bool isVolatile = ST->isVolatile();
2487 bool isNonTemporal = ST->isNonTemporal();
2488 SDValue ValOp = GetWidenedVector(ST->getValue());
2489 DebugLoc dl = ST->getDebugLoc();
2490
2491 EVT StVT = ST->getMemoryVT();
2492 EVT ValVT = ValOp.getValueType();
2493
2494 // It must be true that we the widen vector type is bigger than where
2495 // we need to store.
2496 assert(StVT.isVector() && ValOp.getValueType().isVector());
2497 assert(StVT.bitsLT(ValOp.getValueType()));
2498
2499 // For truncating stores, we can not play the tricks of chopping legal
2500 // vector types and bit cast it to the right type. Instead, we unroll
2501 // the store.
2502 EVT StEltVT = StVT.getVectorElementType();
2503 EVT ValEltVT = ValVT.getVectorElementType();
2504 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2505 unsigned NumElts = StVT.getVectorNumElements();
2506 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2507 DAG.getIntPtrConstant(0));
2508 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2509 ST->getPointerInfo(), StEltVT,
2510 isVolatile, isNonTemporal, Align));
2511 unsigned Offset = Increment;
2512 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2513 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2514 BasePtr, DAG.getIntPtrConstant(Offset));
2515 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2516 DAG.getIntPtrConstant(0));
2517 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2518 ST->getPointerInfo().getWithOffset(Offset),
2519 StEltVT, isVolatile, isNonTemporal,
2520 MinAlign(Align, Offset)));
2521 }
2522 }
2523
2524 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2525 /// input vector must have the same element type as NVT.
ModifyToType(SDValue InOp,EVT NVT)2526 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2527 // Note that InOp might have been widened so it might already have
2528 // the right width or it might need be narrowed.
2529 EVT InVT = InOp.getValueType();
2530 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2531 "input and widen element type must match");
2532 DebugLoc dl = InOp.getDebugLoc();
2533
2534 // Check if InOp already has the right width.
2535 if (InVT == NVT)
2536 return InOp;
2537
2538 unsigned InNumElts = InVT.getVectorNumElements();
2539 unsigned WidenNumElts = NVT.getVectorNumElements();
2540 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2541 unsigned NumConcat = WidenNumElts / InNumElts;
2542 SmallVector<SDValue, 16> Ops(NumConcat);
2543 SDValue UndefVal = DAG.getUNDEF(InVT);
2544 Ops[0] = InOp;
2545 for (unsigned i = 1; i != NumConcat; ++i)
2546 Ops[i] = UndefVal;
2547
2548 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2549 }
2550
2551 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2552 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2553 DAG.getIntPtrConstant(0));
2554
2555 // Fall back to extract and build.
2556 SmallVector<SDValue, 16> Ops(WidenNumElts);
2557 EVT EltVT = NVT.getVectorElementType();
2558 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2559 unsigned Idx;
2560 for (Idx = 0; Idx < MinNumElts; ++Idx)
2561 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2562 DAG.getIntPtrConstant(Idx));
2563
2564 SDValue UndefVal = DAG.getUNDEF(EltVT);
2565 for ( ; Idx < WidenNumElts; ++Idx)
2566 Ops[Idx] = UndefVal;
2567 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
2568 }
2569