| /external/llvm/include/llvm/Support/ |
| D | IRBuilder.h | 503 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
516 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
523 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
536 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
543 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
556 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
563 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
575 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
586 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
592 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
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| /external/llvm/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.cpp | 162 const TargetRegisterClass *RC) { in inClass()
175 const TargetRegisterClass *RC, in storeRegToStackSlot()
212 const TargetRegisterClass *RC, in storeRegToAddr()
222 const TargetRegisterClass *RC, in loadRegFromStackSlot()
253 const TargetRegisterClass *RC, in loadRegFromAddr()
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| D | BlackfinISelDAGToDAG.cpp | 119 static inline bool isCC(const TargetRegisterClass *RC) { in isCC()
123 static inline bool isDCC(const TargetRegisterClass *RC) { in isDCC()
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| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.h | 63 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
79 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
86 ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const { in getOrder()
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| D | LiveStackAnalysis.cpp | 54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
76 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
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| D | AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); in AllocationOrder() local
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| D | PrologEpilogInserter.cpp | 250 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters() local
318 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
345 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
393 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
444 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
837 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg); in scavengeFrameVirtualRegs() local
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| D | VirtRegMap.cpp | 103 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { in createSpillSlot()
132 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot() local
162 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { in getEmergencySpillSlot()
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| D | AggressiveAntiDepBreaker.h | 45 const TargetRegisterClass *RC; member
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| D | MachineLICM.cpp | 628 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in InitRegPressure() local
664 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in UpdateRegPressure() local
678 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in UpdateRegPressure() local
882 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in UpdateBackTraceRegPressure() local
950 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in IsProfitableToHoist() local
963 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in IsProfitableToHoist() local
1023 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI); in ExtractHoistableLoad() local
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| D | StackSlotColoring.cpp | 275 const TargetRegisterClass *RC = LS->getIntervalRegClass(RSS); in ColorSlotsWithFreeRegs() local
421 const TargetRegisterClass *RC = LS->getIntervalRegClass(SS); in ColorSlots() local
524 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI); in PropagateBackward() local
586 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI); in PropagateForward() local
612 const TargetRegisterClass *RC, in UnfoldAndRewriteInstruction()
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| D | VirtRegRewriter.cpp | 445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); in GetRegForReload() local
705 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, in findSuperReg()
787 const TargetRegisterClass* RC = TRI->getMinimalPhysRegClass(Reg); in AddAvailableRegsToLiveIn() local
865 unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC, in GetRegForReload()
1022 const TargetRegisterClass *RC, in FindFreeRegister()
1294 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg); in OptimizeByUnfold2() local
1569 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg); in CommuteToFoldReload() local
1602 const TargetRegisterClass *RC, in SpillRegToStackSlot()
1753 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg); in InsertEmergencySpills() local
1870 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg); in InsertRestores() local
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 172 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
199 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
436 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
449 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, in canCombineSubRegIndices()
515 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
524 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
533 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
545 getRawAllocationOrder(const TargetRegisterClass *RC, in getRawAllocationOrder()
564 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { in avoidWriteAfterWrite()
684 const TargetRegisterClass *RC, in saveScavengerRegister()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 365 const CodeGenRegisterClass &RC = RegisterClasses[i]; in runTargetHeader() local
413 const CodeGenRegisterClass &RC = RegisterClasses[rc]; in runTargetDesc() local
436 const CodeGenRegisterClass &RC = RegisterClasses[rc]; in runTargetDesc() local
469 const CodeGenRegisterClass &RC = RegisterClasses[rc]; in runTargetDesc() local
509 const CodeGenRegisterClass &RC = RegisterClasses[rc]; in runTargetDesc() local
544 const CodeGenRegisterClass &RC = RegisterClasses[rc]; in runTargetDesc() local
580 const CodeGenRegisterClass &RC = RegisterClasses[rc]; in runTargetDesc() local
609 const CodeGenRegisterClass &RC = RegisterClasses[i]; in runTargetDesc() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 590 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in SelectCall() local
614 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); in SelectCall() local
1086 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { in createResultReg()
1091 const TargetRegisterClass* RC) { in FastEmitInst_()
1100 const TargetRegisterClass *RC, in FastEmitInst_r()
1119 const TargetRegisterClass *RC, in FastEmitInst_rr()
1140 const TargetRegisterClass *RC, in FastEmitInst_rrr()
1164 const TargetRegisterClass *RC, in FastEmitInst_ri()
1185 const TargetRegisterClass *RC, in FastEmitInst_rii()
1208 const TargetRegisterClass *RC, in FastEmitInst_rf()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1InstrInfo.cpp | 48 const TargetRegisterClass *RC, in storeRegToStackSlot()
77 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| D | ARMFastISel.cpp | 279 const TargetRegisterClass* RC) { in FastEmitInst_()
288 const TargetRegisterClass *RC, in FastEmitInst_r()
307 const TargetRegisterClass *RC, in FastEmitInst_rr()
329 const TargetRegisterClass *RC, in FastEmitInst_rrr()
354 const TargetRegisterClass *RC, in FastEmitInst_ri()
376 const TargetRegisterClass *RC, in FastEmitInst_rf()
398 const TargetRegisterClass *RC, in FastEmitInst_rri()
423 const TargetRegisterClass *RC, in FastEmitInst_i()
442 const TargetRegisterClass *RC, in FastEmitInst_ii()
663 TargetRegisterClass* RC = TLI.getRegClassFor(VT); in TargetMaterializeAlloca() local
[all …]
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| /external/llvm/lib/Target/ |
| D | TargetRegisterInfo.cpp | 62 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
75 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, in getRegPressureLimit()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 334 const TargetRegisterClass *RC, in StoreRegToStackSlot()
474 const TargetRegisterClass *RC, in storeRegToStackSlot()
500 const TargetRegisterClass *RC, in LoadRegFromStackSlot()
599 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| D | PPCRegisterInfo.cpp | 365 const TargetRegisterClass *RC, int SPAdj) { in findScratchRegister()
415 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; in lowerDynamicAlloc() local
508 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in lowerCRSpilling() local
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 38 const TargetRegisterClass *RC, in storeRegToStackSlot()
67 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.cpp | 95 const TargetRegisterClass *RC, in storeRegToStackSlot()
105 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 289 const TargetRegisterClass *RC, in storeRegToStackSlot()
311 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 46 const TargetRegisterClass *RC, in storeRegToStackSlot()
76 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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