1 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM 2 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 3 * derived from Data Sheet, Copyright Motorola 1984 (!). 4 * It was written to be part of the Linux operating system. 5 */ 6 /* permission is hereby granted to copy, modify and redistribute this code 7 * in terms of the GNU Library General Public License, Version 2 or later, 8 * at your option. 9 */ 10 11 #ifndef _MC146818RTC_H 12 #define _MC146818RTC_H 13 14 #include <asm/io.h> 15 #include <linux/rtc.h> /* get the user-level API */ 16 #include <asm/mc146818rtc.h> /* register access macros */ 17 18 #ifdef __KERNEL__ 19 #include <linux/spinlock.h> /* spinlock_t */ 20 extern spinlock_t rtc_lock; /* serialize CMOS RAM access */ 21 #endif 22 23 /********************************************************************** 24 * register summary 25 **********************************************************************/ 26 #define RTC_SECONDS 0 27 #define RTC_SECONDS_ALARM 1 28 #define RTC_MINUTES 2 29 #define RTC_MINUTES_ALARM 3 30 #define RTC_HOURS 4 31 #define RTC_HOURS_ALARM 5 32 /* RTC_*_alarm is always true if 2 MSBs are set */ 33 # define RTC_ALARM_DONT_CARE 0xC0 34 35 #define RTC_DAY_OF_WEEK 6 36 #define RTC_DAY_OF_MONTH 7 37 #define RTC_MONTH 8 38 #define RTC_YEAR 9 39 40 /* control registers - Moto names 41 */ 42 #define RTC_REG_A 10 43 #define RTC_REG_B 11 44 #define RTC_REG_C 12 45 #define RTC_REG_D 13 46 47 /********************************************************************** 48 * register details 49 **********************************************************************/ 50 #define RTC_FREQ_SELECT RTC_REG_A 51 52 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 53 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 54 * totalling to a max high interval of 2.228 ms. 55 */ 56 # define RTC_UIP 0x80 57 # define RTC_DIV_CTL 0x70 58 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 59 # define RTC_REF_CLCK_4MHZ 0x00 60 # define RTC_REF_CLCK_1MHZ 0x10 61 # define RTC_REF_CLCK_32KHZ 0x20 62 /* 2 values for divider stage reset, others for "testing purposes only" */ 63 # define RTC_DIV_RESET1 0x60 64 # define RTC_DIV_RESET2 0x70 65 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 66 # define RTC_RATE_SELECT 0x0F 67 68 /**********************************************************************/ 69 #define RTC_CONTROL RTC_REG_B 70 # define RTC_SET 0x80 /* disable updates for clock setting */ 71 # define RTC_PIE 0x40 /* periodic interrupt enable */ 72 # define RTC_AIE 0x20 /* alarm interrupt enable */ 73 # define RTC_UIE 0x10 /* update-finished interrupt enable */ 74 # define RTC_SQWE 0x08 /* enable square-wave output */ 75 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 76 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 77 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 78 79 /**********************************************************************/ 80 #define RTC_INTR_FLAGS RTC_REG_C 81 /* caution - cleared by read */ 82 # define RTC_IRQF 0x80 /* any of the following 3 is active */ 83 # define RTC_PF 0x40 84 # define RTC_AF 0x20 85 # define RTC_UF 0x10 86 87 /**********************************************************************/ 88 #define RTC_VALID RTC_REG_D 89 # define RTC_VRT 0x80 /* valid RAM and time */ 90 /**********************************************************************/ 91 92 #ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */ 93 94 #define RTC_IO_EXTENT 0x8 95 #define RTC_IOMAPPED 1 /* Default to I/O mapping. */ 96 97 #endif /* ARCH_RTC_LOCATION */ 98 99 #endif /* _MC146818RTC_H */ 100