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1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines wrappers for the Target class and related global
11 // functionality.  This makes it easier to access the data and provides a single
12 // place that needs to check it for validity.  All of these classes throw
13 // exceptions on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
19 
20 #include "CodeGenRegisters.h"
21 #include "CodeGenInstruction.h"
22 #include "Record.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include <algorithm>
25 
26 namespace llvm {
27 
28 struct CodeGenRegister;
29 class CodeGenTarget;
30 
31 // SelectionDAG node properties.
32 //  SDNPMemOperand: indicates that a node touches memory and therefore must
33 //                  have an associated memory operand that describes the access.
34 enum SDNP {
35   SDNPCommutative,
36   SDNPAssociative,
37   SDNPHasChain,
38   SDNPOutGlue,
39   SDNPInGlue,
40   SDNPOptInGlue,
41   SDNPMayLoad,
42   SDNPMayStore,
43   SDNPSideEffect,
44   SDNPMemOperand,
45   SDNPVariadic,
46   SDNPWantRoot,
47   SDNPWantParent
48 };
49 
50 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
51 /// record corresponds to.
52 MVT::SimpleValueType getValueType(Record *Rec);
53 
54 std::string getName(MVT::SimpleValueType T);
55 std::string getEnumName(MVT::SimpleValueType T);
56 
57 /// getQualifiedName - Return the name of the specified record, with a
58 /// namespace qualifier if the record contains one.
59 std::string getQualifiedName(const Record *R);
60 
61 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
62 ///
63 class CodeGenTarget {
64   RecordKeeper &Records;
65   Record *TargetRec;
66 
67   mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
68   mutable CodeGenRegBank *RegBank;
69   mutable std::vector<Record*> RegAltNameIndices;
70   mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
71   void ReadRegAltNameIndices() const;
72   void ReadInstructions() const;
73   void ReadLegalValueTypes() const;
74 
75   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
76 public:
77   CodeGenTarget(RecordKeeper &Records);
78 
getTargetRecord()79   Record *getTargetRecord() const { return TargetRec; }
80   const std::string &getName() const;
81 
82   /// getInstNamespace - Return the target-specific instruction namespace.
83   ///
84   std::string getInstNamespace() const;
85 
86   /// getInstructionSet - Return the InstructionSet object.
87   ///
88   Record *getInstructionSet() const;
89 
90   /// getAsmParser - Return the AssemblyParser definition for this target.
91   ///
92   Record *getAsmParser() const;
93 
94   /// getAsmWriter - Return the AssemblyWriter definition for this target.
95   ///
96   Record *getAsmWriter() const;
97 
98   /// getRegBank - Return the register bank description.
99   CodeGenRegBank &getRegBank() const;
100 
101   /// getRegisterByName - If there is a register with the specific AsmName,
102   /// return it.
103   const CodeGenRegister *getRegisterByName(StringRef Name) const;
104 
getRegAltNameIndices()105   const std::vector<Record*> &getRegAltNameIndices() const {
106     if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
107     return RegAltNameIndices;
108   }
109 
getRegisterClasses()110   const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
111     return getRegBank().getRegClasses();
112   }
113 
getRegisterClass(Record * R)114   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
115     return *getRegBank().getRegClass(R);
116   }
117 
118   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
119   /// specified physical register.
120   std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
121 
getLegalValueTypes()122   const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
123     if (LegalValueTypes.empty()) ReadLegalValueTypes();
124     return LegalValueTypes;
125   }
126 
127   /// isLegalValueType - Return true if the specified value type is natively
128   /// supported by the target (i.e. there are registers that directly hold it).
isLegalValueType(MVT::SimpleValueType VT)129   bool isLegalValueType(MVT::SimpleValueType VT) const {
130     const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
131     for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
132       if (LegalVTs[i] == VT) return true;
133     return false;
134   }
135 
136 private:
getInstructions()137   DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {
138     if (Instructions.empty()) ReadInstructions();
139     return Instructions;
140   }
141 public:
142 
getInstruction(const Record * InstRec)143   CodeGenInstruction &getInstruction(const Record *InstRec) const {
144     if (Instructions.empty()) ReadInstructions();
145     DenseMap<const Record*, CodeGenInstruction*>::iterator I =
146       Instructions.find(InstRec);
147     assert(I != Instructions.end() && "Not an instruction");
148     return *I->second;
149   }
150 
151   /// getInstructionsByEnumValue - Return all of the instructions defined by the
152   /// target, ordered by their enum value.
153   const std::vector<const CodeGenInstruction*> &
getInstructionsByEnumValue()154   getInstructionsByEnumValue() const {
155     if (InstrsByEnum.empty()) ComputeInstrsByEnum();
156     return InstrsByEnum;
157   }
158 
159   typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
inst_begin()160   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
inst_end()161   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
162 
163 
164   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
165   ///
166   bool isLittleEndianEncoding() const;
167 
168 private:
169   void ComputeInstrsByEnum() const;
170 };
171 
172 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
173 /// tablegen class in TargetSelectionDAG.td
174 class ComplexPattern {
175   MVT::SimpleValueType Ty;
176   unsigned NumOperands;
177   std::string SelectFunc;
178   std::vector<Record*> RootNodes;
179   unsigned Properties; // Node properties
180 public:
ComplexPattern()181   ComplexPattern() : NumOperands(0) {}
182   ComplexPattern(Record *R);
183 
getValueType()184   MVT::SimpleValueType getValueType() const { return Ty; }
getNumOperands()185   unsigned getNumOperands() const { return NumOperands; }
getSelectFunc()186   const std::string &getSelectFunc() const { return SelectFunc; }
getRootNodes()187   const std::vector<Record*> &getRootNodes() const {
188     return RootNodes;
189   }
hasProperty(enum SDNP Prop)190   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
191 };
192 
193 } // End llvm namespace
194 
195 #endif
196