| /external/llvm/lib/Target/ARM/ |
| D | Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool()
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| D | Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool()
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| D | ARMBaseRegisterInfo.cpp | 856 unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| D | ARMBaseInstrInfo.cpp | 658 unsigned Reg, unsigned SubIdx, unsigned State, in AddDReg()
997 unsigned DestReg, unsigned SubIdx, in reMaterialize()
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| D | ARMISelDAGToDAG.cpp | 1903 unsigned SubIdx = ARM::dsub_0; in SelectVLDDup() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 144 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { in getSubRegisterRegClass()
377 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
435 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
741 unsigned SubIdx; variable
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| D | TargetInstrInfo.h | 111 unsigned &SubIdx) const { in isCoalescableExtInstr()
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| /external/llvm/lib/CodeGen/ |
| D | LowerSubregs.cpp | 113 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
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| D | LiveDebugVariables.cpp | 656 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, in renameRegister()
672 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister()
688 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister()
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| D | TwoAddressInstructionPass.cpp | 1246 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1279 unsigned DstReg, unsigned SubIdx, in UpdateRegSequenceSrcs()
1444 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
1507 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
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| D | PeepholeOptimizer.cpp | 134 unsigned SrcReg, DstReg, SubIdx; in OptimizeExtInstr() local
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| D | TargetInstrInfoImpl.cpp | 166 unsigned SubIdx, in reMaterialize()
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| D | VirtRegRewriter.cpp | 706 unsigned SubIdx, const TargetRegisterInfo *TRI) { in findSuperReg()
914 unsigned SubIdx = 0; in GetRegForReload() local
1975 unsigned SubIdx = MI.getOperand(i).getSubReg(); in ProcessUses() local
2546 unsigned SubIdx = MO.getSubReg(); in RewriteMBB() local
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| D | MachineInstr.cpp | 117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg()
1122 unsigned SubIdx, in substituteRegister()
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| D | MachineVerifier.cpp | 714 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
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| D | RegisterCoalescer.cpp | 773 unsigned SubIdx = CP.getSubIdx(); in UpdateRegDefsUses() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 397 unsigned SubIdx, EVT VT) { in getSuperRegisterRegClass()
432 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
483 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
563 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /external/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1446 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; in BuildAliasResultOperands() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 1080 unsigned DestReg, unsigned SubIdx, in reMaterialize()
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