/external/llvm/lib/CodeGen/ |
D | LiveIntervalUnion.h | 174 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query() 190 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init()
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D | LiveRangeEdit.cpp | 36 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
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D | MachineFunction.cpp | 393 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local
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D | TailDuplication.cpp | 220 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local
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D | LiveIntervalAnalysis.cpp | 1891 unsigned VReg = spills[i].vreg; in addIntervalsForSpills() local 1956 unsigned VReg = restores[i].vreg; in addIntervalsForSpills() local
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D | TwoAddressInstructionPass.cpp | 1264 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 244 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local 275 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local 435 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitSubregNode() local 531 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 1789 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_SVR4() local 1808 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_SVR4() local 1974 unsigned VReg; in LowerFormalArguments_Darwin() local 1997 unsigned VReg; in LowerFormalArguments_Darwin() local 2024 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); in LowerFormalArguments_Darwin() local 2038 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_Darwin() local 2073 unsigned VReg; in LowerFormalArguments_Darwin() local 2096 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); in LowerFormalArguments_Darwin() local 2171 unsigned VReg; in LowerFormalArguments_Darwin() local
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/external/llvm/lib/Target/CellSPU/ |
D | SPUISelLowering.cpp | 622 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerLOAD() local 816 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerSTORE() local 1172 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); in LowerFormalArguments() local 1220 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments() local
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 212 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local 324 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local
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/external/llvm/lib/Target/ARM/ |
D | Thumb1RegisterInfo.cpp | 600 unsigned VReg = 0; in eliminateFrameIndex() local
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D | ARMISelLowering.cpp | 2420 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in VarArgStyleRegisters() local
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 329 unsigned VReg = RegInfo.createVirtualRegister(RC); in LowerCCCArguments() local
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/external/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1109 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local 1160 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local
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/external/llvm/lib/Target/Alpha/ |
D | AlphaISelLowering.cpp | 42 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn() local
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 336 unsigned VReg = in LowerCCCArguments() local
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 547 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn() local
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 1858 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], in LowerFormalArguments() local 1885 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], in LowerFormalArguments() local
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