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1  /*
2   * ARM virtual CPU header
3   *
4   *  Copyright (c) 2003 Fabrice Bellard
5   *
6   * This library is free software; you can redistribute it and/or
7   * modify it under the terms of the GNU Lesser General Public
8   * License as published by the Free Software Foundation; either
9   * version 2 of the License, or (at your option) any later version.
10   *
11   * This library is distributed in the hope that it will be useful,
12   * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14   * Lesser General Public License for more details.
15   *
16   * You should have received a copy of the GNU Lesser General Public
17   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18   */
19  #ifndef CPU_ARM_H
20  #define CPU_ARM_H
21  
22  #define TARGET_LONG_BITS 32
23  
24  #define ELF_MACHINE	EM_ARM
25  
26  #define CPUState struct CPUARMState
27  
28  #include "config.h"
29  #include "qemu-common.h"
30  #include "cpu-defs.h"
31  
32  #include "softfloat.h"
33  
34  #define TARGET_HAS_ICE 1
35  
36  #define EXCP_UDEF            1   /* undefined instruction */
37  #define EXCP_SWI             2   /* software interrupt */
38  #define EXCP_PREFETCH_ABORT  3
39  #define EXCP_DATA_ABORT      4
40  #define EXCP_IRQ             5
41  #define EXCP_FIQ             6
42  #define EXCP_BKPT            7
43  #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
44  #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
45  #define EXCP_STREX          10
46  #define EXCP_SMC            11   /* secure monitor call */
47  
48  #define ARMV7M_EXCP_RESET   1
49  #define ARMV7M_EXCP_NMI     2
50  #define ARMV7M_EXCP_HARD    3
51  #define ARMV7M_EXCP_MEM     4
52  #define ARMV7M_EXCP_BUS     5
53  #define ARMV7M_EXCP_USAGE   6
54  #define ARMV7M_EXCP_SVC     11
55  #define ARMV7M_EXCP_DEBUG   12
56  #define ARMV7M_EXCP_PENDSV  14
57  #define ARMV7M_EXCP_SYSTICK 15
58  
59  /* ARM-specific interrupt pending bits.  */
60  #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
61  
62  
63  typedef void ARMWriteCPFunc(void *opaque, int cp_info,
64                              int srcreg, int operand, uint32_t value,
65                              void *retaddr);
66  typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
67                                 int dstreg, int operand,
68                                 void *retaddr);
69  
70  struct arm_boot_info;
71  
72  #define NB_MMU_MODES 2
73  
74  /* We currently assume float and double are IEEE single and double
75     precision respectively.
76     Doing runtime conversions is tricky because VFP registers may contain
77     integer values (eg. as the result of a FTOSI instruction).
78     s<2n> maps to the least significant half of d<n>
79     s<2n+1> maps to the most significant half of d<n>
80   */
81  
82  typedef struct CPUARMState {
83      /* Regs for current mode.  */
84      uint32_t regs[16];
85      /* Frequently accessed CPSR bits are stored separately for efficiently.
86         This contains all the other bits.  Use cpsr_{read,write} to access
87         the whole CPSR.  */
88      uint32_t uncached_cpsr;
89      uint32_t spsr;
90  
91      /* Banked registers.  */
92      uint32_t banked_spsr[7];
93      uint32_t banked_r13[7];
94      uint32_t banked_r14[7];
95  
96      /* These hold r8-r12.  */
97      uint32_t usr_regs[5];
98      uint32_t fiq_regs[5];
99  
100      /* cpsr flag cache for faster execution */
101      uint32_t CF; /* 0 or 1 */
102      uint32_t VF; /* V is the bit 31. All other bits are undefined */
103      uint32_t NF; /* N is bit 31. All other bits are undefined.  */
104      uint32_t ZF; /* Z set if zero.  */
105      uint32_t QF; /* 0 or 1 */
106      uint32_t GE; /* cpsr[19:16] */
107      uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
108      uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
109  
110      /* System control coprocessor (cp15) */
111      struct {
112          uint32_t c0_cpuid;
113          uint32_t c0_cachetype;
114          uint32_t c0_ccsid[16]; /* Cache size.  */
115          uint32_t c0_clid; /* Cache level.  */
116          uint32_t c0_cssel; /* Cache size selection.  */
117          uint32_t c0_c1[8]; /* Feature registers.  */
118          uint32_t c0_c2[8]; /* Instruction set registers.  */
119          uint32_t c1_sys; /* System control register.  */
120          uint32_t c1_coproc; /* Coprocessor access register.  */
121          uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
122          uint32_t c1_secfg; /* Secure configuration register. */
123          uint32_t c1_sedbg; /* Secure debug enable register. */
124          uint32_t c1_nseac; /* Non-secure access control register. */
125          uint32_t c2_base0; /* MMU translation table base 0.  */
126          uint32_t c2_base1; /* MMU translation table base 1.  */
127          uint32_t c2_control; /* MMU translation table base control.  */
128          uint32_t c2_mask; /* MMU translation table base selection mask.  */
129          uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
130          uint32_t c2_data; /* MPU data cachable bits.  */
131          uint32_t c2_insn; /* MPU instruction cachable bits.  */
132          uint32_t c3; /* MMU domain access control register
133                          MPU write buffer control.  */
134          uint32_t c5_insn; /* Fault status registers.  */
135          uint32_t c5_data;
136          uint32_t c6_region[8]; /* MPU base/size registers.  */
137          uint32_t c6_insn; /* Fault address registers.  */
138          uint32_t c6_data;
139          uint32_t c7_par;  /* Translation result. */
140          uint32_t c9_insn; /* Cache lockdown registers.  */
141          uint32_t c9_data;
142          uint32_t c9_pmcr_data; /* Performance Monitor Control Register */
143          uint32_t c9_useren; /* user enable register */
144          uint32_t c9_inten; /* interrupt enable set/clear register */
145          uint32_t c12_vbar; /* secure/nonsecure vector base address register. */
146          uint32_t c12_mvbar; /* monitor vector base address register. */
147          uint32_t c13_fcse; /* FCSE PID.  */
148          uint32_t c13_context; /* Context ID.  */
149          uint32_t c13_tls1; /* User RW Thread register.  */
150          uint32_t c13_tls2; /* User RO Thread register.  */
151          uint32_t c13_tls3; /* Privileged Thread register.  */
152          uint32_t c15_cpar; /* XScale Coprocessor Access Register */
153          uint32_t c15_ticonfig; /* TI925T configuration byte.  */
154          uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
155          uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
156          uint32_t c15_threadid; /* TI debugger thread-ID.  */
157      } cp15;
158  
159      struct {
160          uint32_t other_sp;
161          uint32_t vecbase;
162          uint32_t basepri;
163          uint32_t control;
164          int current_sp;
165          int exception;
166          int pending_exception;
167      } v7m;
168  
169      /* Minimal set of debug coprocessor state (cp14) */
170      uint32_t cp14_dbgdidr;
171  
172      /* Thumb-2 EE state.  */
173      uint32_t teecr;
174      uint32_t teehbr;
175  
176      /* Internal CPU feature flags.  */
177      uint32_t features;
178  
179      /* VFP coprocessor state.  */
180      struct {
181          float64 regs[32];
182  
183          uint32_t xregs[16];
184          /* We store these fpcsr fields separately for convenience.  */
185          int vec_len;
186          int vec_stride;
187  
188          /* scratch space when Tn are not sufficient.  */
189          uint32_t scratch[8];
190  
191          /* fp_status is the "normal" fp status. standard_fp_status retains
192           * values corresponding to the ARM "Standard FPSCR Value", ie
193           * default-NaN, flush-to-zero, round-to-nearest and is used by
194           * any operations (generally Neon) which the architecture defines
195           * as controlled by the standard FPSCR value rather than the FPSCR.
196           *
197           * To avoid having to transfer exception bits around, we simply
198           * say that the FPSCR cumulative exception flags are the logical
199           * OR of the flags in the two fp statuses. This relies on the
200           * only thing which needs to read the exception flags being
201           * an explicit FPSCR read.
202           */
203          float_status fp_status;
204          float_status standard_fp_status;
205      } vfp;
206      uint32_t exclusive_addr;
207      uint32_t exclusive_val;
208      uint32_t exclusive_high;
209  #if defined(CONFIG_USER_ONLY)
210      uint32_t exclusive_test;
211      uint32_t exclusive_info;
212  #endif
213  
214      /* iwMMXt coprocessor state.  */
215      struct {
216          uint64_t regs[16];
217          uint64_t val;
218  
219          uint32_t cregs[16];
220      } iwmmxt;
221  
222  #if defined(CONFIG_USER_ONLY)
223      /* For usermode syscall translation.  */
224      int eabi;
225  #endif
226  
227      CPU_COMMON
228  
229      /* These fields after the common ones so they are preserved on reset.  */
230  
231      /* Coprocessor IO used by peripherals */
232      struct {
233          ARMReadCPFunc *cp_read;
234          ARMWriteCPFunc *cp_write;
235          void *opaque;
236      } cp[15];
237      void *nvic;
238      struct arm_boot_info *boot_info;
239  } CPUARMState;
240  
241  CPUARMState *cpu_arm_init(const char *cpu_model);
242  void arm_translate_init(void);
243  int cpu_arm_exec(CPUARMState *s);
244  void cpu_arm_close(CPUARMState *s);
245  void do_interrupt(CPUARMState *);
246  void switch_mode(CPUARMState *, int);
247  uint32_t do_arm_semihosting(CPUARMState *env);
248  
249  /* you can call this signal handler from your SIGBUS and SIGSEGV
250     signal handlers to inform the virtual CPU of exceptions. non zero
251     is returned if the signal was handled by the virtual CPU.  */
252  int cpu_arm_signal_handler(int host_signum, void *pinfo,
253                             void *puc);
254  int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
255                                int mmu_idx, int is_softmuu);
256  #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
257  
cpu_set_tls(CPUARMState * env,target_ulong newtls)258  static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
259  {
260    env->cp15.c13_tls2 = newtls;
261  }
262  
263  #define CPSR_M (0x1f)
264  #define CPSR_T (1 << 5)
265  #define CPSR_F (1 << 6)
266  #define CPSR_I (1 << 7)
267  #define CPSR_A (1 << 8)
268  #define CPSR_E (1 << 9)
269  #define CPSR_IT_2_7 (0xfc00)
270  #define CPSR_GE (0xf << 16)
271  #define CPSR_RESERVED (0xf << 20)
272  #define CPSR_J (1 << 24)
273  #define CPSR_IT_0_1 (3 << 25)
274  #define CPSR_Q (1 << 27)
275  #define CPSR_V (1 << 28)
276  #define CPSR_C (1 << 29)
277  #define CPSR_Z (1 << 30)
278  #define CPSR_N (1 << 31)
279  #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
280  
281  #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
282  #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
283  /* Bits writable in user mode.  */
284  #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
285  /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
286  #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
287  
288  /* Return the current CPSR value.  */
289  uint32_t cpsr_read(CPUARMState *env);
290  /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
291  void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
292  
293  /* Return the current xPSR value.  */
xpsr_read(CPUARMState * env)294  static inline uint32_t xpsr_read(CPUARMState *env)
295  {
296      int ZF;
297      ZF = (env->ZF == 0);
298      return (env->NF & 0x80000000) | (ZF << 30)
299          | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
300          | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
301          | ((env->condexec_bits & 0xfc) << 8)
302          | env->v7m.exception;
303  }
304  
305  /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
xpsr_write(CPUARMState * env,uint32_t val,uint32_t mask)306  static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
307  {
308      if (mask & CPSR_NZCV) {
309          env->ZF = (~val) & CPSR_Z;
310          env->NF = val;
311          env->CF = (val >> 29) & 1;
312          env->VF = (val << 3) & 0x80000000;
313      }
314      if (mask & CPSR_Q)
315          env->QF = ((val & CPSR_Q) != 0);
316      if (mask & (1 << 24))
317          env->thumb = ((val & (1 << 24)) != 0);
318      if (mask & CPSR_IT_0_1) {
319          env->condexec_bits &= ~3;
320          env->condexec_bits |= (val >> 25) & 3;
321      }
322      if (mask & CPSR_IT_2_7) {
323          env->condexec_bits &= 3;
324          env->condexec_bits |= (val >> 8) & 0xfc;
325      }
326      if (mask & 0x1ff) {
327          env->v7m.exception = val & 0x1ff;
328      }
329  }
330  
331  /* Return the current FPSCR value.  */
332  uint32_t vfp_get_fpscr(CPUARMState *env);
333  void vfp_set_fpscr(CPUARMState *env, uint32_t val);
334  
335  enum arm_cpu_mode {
336    ARM_CPU_MODE_USR = 0x10,
337    ARM_CPU_MODE_FIQ = 0x11,
338    ARM_CPU_MODE_IRQ = 0x12,
339    ARM_CPU_MODE_SVC = 0x13,
340    ARM_CPU_MODE_SMC = 0x16,
341    ARM_CPU_MODE_ABT = 0x17,
342    ARM_CPU_MODE_UND = 0x1b,
343    ARM_CPU_MODE_SYS = 0x1f
344  };
345  
346  /* VFP system registers.  */
347  #define ARM_VFP_FPSID   0
348  #define ARM_VFP_FPSCR   1
349  #define ARM_VFP_MVFR1   6
350  #define ARM_VFP_MVFR0   7
351  #define ARM_VFP_FPEXC   8
352  #define ARM_VFP_FPINST  9
353  #define ARM_VFP_FPINST2 10
354  
355  /* iwMMXt coprocessor control registers.  */
356  #define ARM_IWMMXT_wCID		0
357  #define ARM_IWMMXT_wCon		1
358  #define ARM_IWMMXT_wCSSF	2
359  #define ARM_IWMMXT_wCASF	3
360  #define ARM_IWMMXT_wCGR0	8
361  #define ARM_IWMMXT_wCGR1	9
362  #define ARM_IWMMXT_wCGR2	10
363  #define ARM_IWMMXT_wCGR3	11
364  
365  enum arm_features {
366      ARM_FEATURE_VFP,
367      ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
368      ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
369      ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
370      ARM_FEATURE_V6,
371      ARM_FEATURE_V6K,
372      ARM_FEATURE_V7,
373      ARM_FEATURE_THUMB2,
374      ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
375      ARM_FEATURE_VFP3,
376      ARM_FEATURE_VFP_FP16,
377      ARM_FEATURE_NEON,
378      ARM_FEATURE_DIV,
379      ARM_FEATURE_M, /* Microcontroller profile.  */
380      ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
381      ARM_FEATURE_THUMB2EE,
382      ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
383      ARM_FEATURE_V4T,
384      ARM_FEATURE_V5,
385      ARM_FEATURE_STRONGARM,
386      ARM_FEATURE_TRUSTZONE, /* TrustZone Security Extensions. */
387  };
388  
arm_feature(CPUARMState * env,int feature)389  static inline int arm_feature(CPUARMState *env, int feature)
390  {
391      return (env->features & (1u << feature)) != 0;
392  }
393  
394  void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
395  
396  /* Interface between CPU and Interrupt controller.  */
397  void armv7m_nvic_set_pending(void *opaque, int irq);
398  int armv7m_nvic_acknowledge_irq(void *opaque);
399  void armv7m_nvic_complete_irq(void *opaque, int irq);
400  
401  void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
402                         ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
403                         void *opaque);
404  
405  /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
406     Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
407     conventional cores (ie. Application or Realtime profile).  */
408  
409  #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
410  #define ARM_CPUID(env) (env->cp15.c0_cpuid)
411  
412  #define ARM_CPUID_ARM1026     0x4106a262
413  #define ARM_CPUID_ARM926      0x41069265
414  #define ARM_CPUID_ARM946      0x41059461
415  #define ARM_CPUID_TI915T      0x54029152
416  #define ARM_CPUID_TI925T      0x54029252
417  #define ARM_CPUID_SA1100      0x4401A11B
418  #define ARM_CPUID_SA1110      0x6901B119
419  #define ARM_CPUID_PXA250      0x69052100
420  #define ARM_CPUID_PXA255      0x69052d00
421  #define ARM_CPUID_PXA260      0x69052903
422  #define ARM_CPUID_PXA261      0x69052d05
423  #define ARM_CPUID_PXA262      0x69052d06
424  #define ARM_CPUID_PXA270      0x69054110
425  #define ARM_CPUID_PXA270_A0   0x69054110
426  #define ARM_CPUID_PXA270_A1   0x69054111
427  #define ARM_CPUID_PXA270_B0   0x69054112
428  #define ARM_CPUID_PXA270_B1   0x69054113
429  #define ARM_CPUID_PXA270_C0   0x69054114
430  #define ARM_CPUID_PXA270_C5   0x69054117
431  #define ARM_CPUID_ARM1136     0x4117b363
432  #define ARM_CPUID_ARM1136_R2  0x4107b362
433  #define ARM_CPUID_ARM11MPCORE 0x410fb022
434  #define ARM_CPUID_CORTEXA8    0x410fc080
435  #define ARM_CPUID_CORTEXA8_R2 0x412fc083
436  #define ARM_CPUID_CORTEXA9    0x410fc090
437  #define ARM_CPUID_CORTEXM3    0x410fc231
438  #define ARM_CPUID_ANY         0xffffffff
439  
440  #if defined(CONFIG_USER_ONLY)
441  #define TARGET_PAGE_BITS 12
442  #else
443  /* The ARM MMU allows 1k pages.  */
444  /* ??? Linux doesn't actually use these, and they're deprecated in recent
445     architecture revisions.  Maybe a configure option to disable them.  */
446  #define TARGET_PAGE_BITS 10
447  #endif
448  
449  #define TARGET_PHYS_ADDR_SPACE_BITS 32
450  #define TARGET_VIRT_ADDR_SPACE_BITS 32
451  
452  #define cpu_init cpu_arm_init
453  #define cpu_exec cpu_arm_exec
454  #define cpu_gen_code cpu_arm_gen_code
455  #define cpu_signal_handler cpu_arm_signal_handler
456  #define cpu_list arm_cpu_list
457  
458  #define CPU_SAVE_VERSION 3
459  
460  /* MMU modes definitions */
461  #define MMU_MODE0_SUFFIX _kernel
462  #define MMU_MODE1_SUFFIX _user
463  #define MMU_USER_IDX 1
cpu_mmu_index(CPUState * env)464  static inline int cpu_mmu_index (CPUState *env)
465  {
466      return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
467  }
468  
is_cpu_user(CPUState * env)469  static inline int is_cpu_user (CPUState *env)
470  {
471  #ifdef CONFIG_USER_ONLY
472      return 1;
473  #else
474      return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR;
475  #endif  // CONFIG_USER_ONLY
476  }
477  
478  #if defined(CONFIG_USER_ONLY)
cpu_clone_regs(CPUState * env,target_ulong newsp)479  static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
480  {
481      if (newsp)
482          env->regs[13] = newsp;
483      env->regs[0] = 0;
484  }
485  #endif
486  
487  #include "cpu-all.h"
488  
489  /* Bit usage in the TB flags field: */
490  #define ARM_TBFLAG_THUMB_SHIFT      0
491  #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
492  #define ARM_TBFLAG_VECLEN_SHIFT     1
493  #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
494  #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
495  #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
496  #define ARM_TBFLAG_PRIV_SHIFT       6
497  #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
498  #define ARM_TBFLAG_VFPEN_SHIFT      7
499  #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
500  #define ARM_TBFLAG_CONDEXEC_SHIFT   8
501  #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
502  /* Bits 31..16 are currently unused. */
503  
504  /* some convenience accessor macros */
505  #define ARM_TBFLAG_THUMB(F) \
506      (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
507  #define ARM_TBFLAG_VECLEN(F) \
508      (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
509  #define ARM_TBFLAG_VECSTRIDE(F) \
510      (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
511  #define ARM_TBFLAG_PRIV(F) \
512      (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
513  #define ARM_TBFLAG_VFPEN(F) \
514      (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
515  #define ARM_TBFLAG_CONDEXEC(F) \
516      (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
517  
cpu_get_tb_cpu_state(CPUState * env,target_ulong * pc,target_ulong * cs_base,int * flags)518  static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
519                                          target_ulong *cs_base, int *flags)
520  {
521      int privmode;
522      *pc = env->regs[15];
523      *cs_base = 0;
524      *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
525          | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
526          | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
527          | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
528      if (arm_feature(env, ARM_FEATURE_M)) {
529          privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
530      } else {
531          privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
532      }
533      if (privmode) {
534          *flags |= ARM_TBFLAG_PRIV_MASK;
535      }
536      if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
537          *flags |= ARM_TBFLAG_VFPEN_MASK;
538      }
539  }
540  
541  #endif
542