1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides X86 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "llvm/MC/MachineLocation.h"
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Support/Host.h"
23
24 #define GET_REGINFO_MC_DESC
25 #include "X86GenRegisterInfo.inc"
26
27 #define GET_INSTRINFO_MC_DESC
28 #include "X86GenInstrInfo.inc"
29
30 #define GET_SUBTARGETINFO_MC_DESC
31 #include "X86GenSubtargetInfo.inc"
32
33 using namespace llvm;
34
35
ParseX86Triple(StringRef TT)36 std::string X86_MC::ParseX86Triple(StringRef TT) {
37 Triple TheTriple(TT);
38 if (TheTriple.getArch() == Triple::x86_64)
39 return "+64bit-mode";
40 return "-64bit-mode";
41 }
42
43 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
44 /// specified arguments. If we can't run cpuid on the host, return true.
GetCpuIDAndInfo(unsigned value,unsigned * rEAX,unsigned * rEBX,unsigned * rECX,unsigned * rEDX)45 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
46 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
47 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
48 #if defined(__GNUC__)
49 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
50 asm ("movq\t%%rbx, %%rsi\n\t"
51 "cpuid\n\t"
52 "xchgq\t%%rbx, %%rsi\n\t"
53 : "=a" (*rEAX),
54 "=S" (*rEBX),
55 "=c" (*rECX),
56 "=d" (*rEDX)
57 : "a" (value));
58 return false;
59 #elif defined(_MSC_VER)
60 int registers[4];
61 __cpuid(registers, value);
62 *rEAX = registers[0];
63 *rEBX = registers[1];
64 *rECX = registers[2];
65 *rEDX = registers[3];
66 return false;
67 #endif
68 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
69 #if defined(__GNUC__)
70 asm ("movl\t%%ebx, %%esi\n\t"
71 "cpuid\n\t"
72 "xchgl\t%%ebx, %%esi\n\t"
73 : "=a" (*rEAX),
74 "=S" (*rEBX),
75 "=c" (*rECX),
76 "=d" (*rEDX)
77 : "a" (value));
78 return false;
79 #elif defined(_MSC_VER)
80 __asm {
81 mov eax,value
82 cpuid
83 mov esi,rEAX
84 mov dword ptr [esi],eax
85 mov esi,rEBX
86 mov dword ptr [esi],ebx
87 mov esi,rECX
88 mov dword ptr [esi],ecx
89 mov esi,rEDX
90 mov dword ptr [esi],edx
91 }
92 return false;
93 #endif
94 #endif
95 return true;
96 }
97
DetectFamilyModel(unsigned EAX,unsigned & Family,unsigned & Model)98 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
99 unsigned &Model) {
100 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
101 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
102 if (Family == 6 || Family == 0xf) {
103 if (Family == 0xf)
104 // Examine extended family ID if family ID is F.
105 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
106 // Examine extended model ID if family ID is 6 or F.
107 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
108 }
109 }
110
getDwarfRegFlavour(StringRef TT,bool isEH)111 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
112 Triple TheTriple(TT);
113 if (TheTriple.getArch() == Triple::x86_64)
114 return DWARFFlavour::X86_64;
115
116 if (TheTriple.isOSDarwin())
117 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
118 if (TheTriple.getOS() == Triple::MinGW32 ||
119 TheTriple.getOS() == Triple::Cygwin)
120 // Unsupported by now, just quick fallback
121 return DWARFFlavour::X86_32_Generic;
122 return DWARFFlavour::X86_32_Generic;
123 }
124
125 /// getX86RegNum - This function maps LLVM register identifiers to their X86
126 /// specific numbering, which is used in various places encoding instructions.
getX86RegNum(unsigned RegNo)127 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
128 switch(RegNo) {
129 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
130 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
131 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
132 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
133 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
134 return N86::ESP;
135 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
136 return N86::EBP;
137 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
138 return N86::ESI;
139 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
140 return N86::EDI;
141
142 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
143 return N86::EAX;
144 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
145 return N86::ECX;
146 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
147 return N86::EDX;
148 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
149 return N86::EBX;
150 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
151 return N86::ESP;
152 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
153 return N86::EBP;
154 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
155 return N86::ESI;
156 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
157 return N86::EDI;
158
159 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
160 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
161 return RegNo-X86::ST0;
162
163 case X86::XMM0: case X86::XMM8:
164 case X86::YMM0: case X86::YMM8: case X86::MM0:
165 return 0;
166 case X86::XMM1: case X86::XMM9:
167 case X86::YMM1: case X86::YMM9: case X86::MM1:
168 return 1;
169 case X86::XMM2: case X86::XMM10:
170 case X86::YMM2: case X86::YMM10: case X86::MM2:
171 return 2;
172 case X86::XMM3: case X86::XMM11:
173 case X86::YMM3: case X86::YMM11: case X86::MM3:
174 return 3;
175 case X86::XMM4: case X86::XMM12:
176 case X86::YMM4: case X86::YMM12: case X86::MM4:
177 return 4;
178 case X86::XMM5: case X86::XMM13:
179 case X86::YMM5: case X86::YMM13: case X86::MM5:
180 return 5;
181 case X86::XMM6: case X86::XMM14:
182 case X86::YMM6: case X86::YMM14: case X86::MM6:
183 return 6;
184 case X86::XMM7: case X86::XMM15:
185 case X86::YMM7: case X86::YMM15: case X86::MM7:
186 return 7;
187
188 case X86::ES: return 0;
189 case X86::CS: return 1;
190 case X86::SS: return 2;
191 case X86::DS: return 3;
192 case X86::FS: return 4;
193 case X86::GS: return 5;
194
195 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
196 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
197 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
198 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
199 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
200 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
201 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
202 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
203
204 // Pseudo index registers are equivalent to a "none"
205 // scaled index (See Intel Manual 2A, table 2-3)
206 case X86::EIZ:
207 case X86::RIZ:
208 return 4;
209
210 default:
211 assert((int(RegNo) > 0) && "Unknown physical register!");
212 return 0;
213 }
214 }
215
InitLLVM2SEHRegisterMapping(MCRegisterInfo * MRI)216 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
217 // FIXME: TableGen these.
218 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
219 int SEH = X86_MC::getX86RegNum(Reg);
220 switch (Reg) {
221 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
222 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
223 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
224 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
225 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
226 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
227 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
228 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
229 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
230 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
231 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
232 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
233 SEH += 8;
234 break;
235 }
236 MRI->mapLLVMRegToSEHReg(Reg, SEH);
237 }
238 }
239
createX86MCSubtargetInfo(StringRef TT,StringRef CPU,StringRef FS)240 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
241 StringRef FS) {
242 std::string ArchFS = X86_MC::ParseX86Triple(TT);
243 if (!FS.empty()) {
244 if (!ArchFS.empty())
245 ArchFS = ArchFS + "," + FS.str();
246 else
247 ArchFS = FS;
248 }
249
250 std::string CPUName = CPU;
251 if (CPUName.empty()) {
252 #if defined (__x86_64__) || defined(__i386__)
253 CPUName = sys::getHostCPUName();
254 #else
255 CPUName = "generic";
256 #endif
257 }
258
259 MCSubtargetInfo *X = new MCSubtargetInfo();
260 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
261 return X;
262 }
263
264 // Force static initialization.
LLVMInitializeX86MCSubtargetInfo()265 extern "C" void LLVMInitializeX86MCSubtargetInfo() {
266 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
267 X86_MC::createX86MCSubtargetInfo);
268 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
269 X86_MC::createX86MCSubtargetInfo);
270 }
271
createX86MCInstrInfo()272 static MCInstrInfo *createX86MCInstrInfo() {
273 MCInstrInfo *X = new MCInstrInfo();
274 InitX86MCInstrInfo(X);
275 return X;
276 }
277
LLVMInitializeX86MCInstrInfo()278 extern "C" void LLVMInitializeX86MCInstrInfo() {
279 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
280 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
281 }
282
createX86MCRegisterInfo(StringRef TT)283 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
284 Triple TheTriple(TT);
285 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
286 ? X86::RIP // Should have dwarf #16.
287 : X86::EIP; // Should have dwarf #8.
288
289 MCRegisterInfo *X = new MCRegisterInfo();
290 InitX86MCRegisterInfo(X, RA,
291 X86_MC::getDwarfRegFlavour(TT, false),
292 X86_MC::getDwarfRegFlavour(TT, true));
293 X86_MC::InitLLVM2SEHRegisterMapping(X);
294 return X;
295 }
296
LLVMInitializeX86MCRegisterInfo()297 extern "C" void LLVMInitializeX86MCRegisterInfo() {
298 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
299 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
300 }
301
302
createX86MCAsmInfo(const Target & T,StringRef TT)303 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
304 Triple TheTriple(TT);
305 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
306
307 MCAsmInfo *MAI;
308 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
309 if (is64Bit)
310 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
311 else
312 MAI = new X86MCAsmInfoDarwin(TheTriple);
313 } else if (TheTriple.isOSWindows()) {
314 MAI = new X86MCAsmInfoCOFF(TheTriple);
315 } else {
316 MAI = new X86ELFMCAsmInfo(TheTriple);
317 }
318
319 // Initialize initial frame state.
320 // Calculate amount of bytes used for return address storing
321 int stackGrowth = is64Bit ? -8 : -4;
322
323 // Initial state of the frame pointer is esp+stackGrowth.
324 MachineLocation Dst(MachineLocation::VirtualFP);
325 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
326 MAI->addInitialFrameState(0, Dst, Src);
327
328 // Add return address to move list
329 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
330 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
331 MAI->addInitialFrameState(0, CSDst, CSSrc);
332
333 return MAI;
334 }
335
LLVMInitializeX86MCAsmInfo()336 extern "C" void LLVMInitializeX86MCAsmInfo() {
337 // Register the target asm info.
338 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
339 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
340 }
341
createX86MCCodeGenInfo(StringRef TT,Reloc::Model RM)342 MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
343 MCCodeGenInfo *X = new MCCodeGenInfo();
344
345 Triple T(TT);
346 bool is64Bit = T.getArch() == Triple::x86_64;
347
348 if (RM == Reloc::Default) {
349 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
350 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
351 // use static relocation model by default.
352 if (T.isOSDarwin()) {
353 if (is64Bit)
354 RM = Reloc::PIC_;
355 else
356 RM = Reloc::DynamicNoPIC;
357 } else if (T.isOSWindows() && is64Bit)
358 RM = Reloc::PIC_;
359 else
360 RM = Reloc::Static;
361 }
362
363 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
364 // is defined as a model for code which may be used in static or dynamic
365 // executables but not necessarily a shared library. On X86-32 we just
366 // compile in -static mode, in x86-64 we use PIC.
367 if (RM == Reloc::DynamicNoPIC) {
368 if (is64Bit)
369 RM = Reloc::PIC_;
370 else if (!T.isOSDarwin())
371 RM = Reloc::Static;
372 }
373
374 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
375 // the Mach-O file format doesn't support it.
376 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
377 RM = Reloc::PIC_;
378
379 X->InitMCCodeGenInfo(RM);
380 return X;
381 }
382
LLVMInitializeX86MCCodeGenInfo()383 extern "C" void LLVMInitializeX86MCCodeGenInfo() {
384 // Register the target asm info.
385 RegisterMCCodeGenInfoFn A(TheX86_32Target, createX86MCCodeGenInfo);
386 RegisterMCCodeGenInfoFn B(TheX86_64Target, createX86MCCodeGenInfo);
387 }
388